Semiconductor device and method of manufacturing the same

Abstract

According to an embodiment, a semiconductor device includes a plurality of first semiconductor regions that extend in a first direction and are arranged in a direction intersecting the first direction, and each element separation region that is provided between the plurality of first semiconductor regions. The element separation region includes a first element separation portion that is formed to a first depth from an upper surface of the first semiconductor region and a second element separation portion that is formed from the first depth to a second depth more than the first depth and electrically insulates between adjacent elements.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a plurality of first semiconductor regions that extend in a first direction and are arranged in a direction intersecting the first direction; and   an element separation region that is provided between the plurality of first semiconductor regions,   wherein the element separation region includes:
 a first element separation portion that is formed to a first depth from an upper surface of the first semiconductor region; and 
 a second element separation portion that is formed from the first depth to a second depth more than the first depth and electrically insulates between adjacent elements. 
   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising:
 a plurality of control gate electrodes that are provided above the plurality of first semiconductor regions, extend in a second direction different from the first direction, and are arranged in a direction intersecting the second direction;   a charge trapping layer that is provided at intersections of the plurality of first semiconductor regions and the plurality of control gate electrodes;   a first gate insulating film that is provided between the charge trapping layer and each of the plurality of first semiconductor regions; and   a second gate insulating film that is provided between the charge trapping layer and each of the plurality of control gate electrodes,   wherein the width of the second element separation portion in the second direction at a position where the first element separation portion is connected to the second element separation portion is less than the width of the first element separation portion in the second direction at the position.   
     
     
         3 . The semiconductor device according to  claim 2 , further comprising:
 a second semiconductor region that covers at least a portion of a lower end of the element separation region and a side surface of the element separation region connected to the lower end,   wherein the conduction type of the second semiconductor region is different from that of the plurality of first semiconductor regions.   
     
     
         4 . The semiconductor device according to  claim 2 ,
 wherein the first element separation portion and the second element separation portion are made of the same insulating material.   
     
     
         5 . The semiconductor device according to  claim 2 ,
 wherein the first element separation portion includes a first insulating film that covers the side surfaces of the first semiconductor region, the first gate insulating film, and the charge trapping layer in a first trench, and a second insulating film that covers a region other than the region in which the first insulating film and is made of a material different from the first insulating film, and   the second element separation portion includes a third insulating film that fills an entire second trench, and the third insulating film is made of a same material as the first insulating film.   
     
     
         6 . The semiconductor device according to  claim 3 ,
 wherein the second element separation portion is made of an insulating material including an impurity of the same conduction type as an impurity in the second semiconductor region.   
     
     
         7 . The semiconductor device according to  claim 1 ,
 wherein the first semiconductor region includes:
 a first impurity diffusion layer which is formed from the first depth to the second depth and in which an impurity with a predetermined conduction type is diffused; and 
 a second impurity diffusion layer which is formed from an upper surface of the first semiconductor region to a third depth less than the first depth and in which an impurity with a predetermined conduction type is diffused, and 
   the element separation region includes:
 a first diffusion source layer which is an insulating film that is provided from the first depth to the second depth and includes an impurity of the same conduction type as the impurity in the first impurity diffusion layer at a first concentration; and 
 a second diffusion source layer which is an insulating film that is provided from the upper surface of the first semiconductor region to the third depth and includes an impurity of the same conduction type as the impurity in the second impurity diffusion layer at a second concentration. 
   
     
     
         8 . The semiconductor device according to  claim 7 ,
 wherein the first semiconductor region further includes a third impurity diffusion layer which is provided between the first impurity diffusion layer and the second impurity diffusion layer and in which an impurity of a predetermined conduction type is diffused in a region below the second impurity diffusion layer.   
     
     
         9 . The semiconductor device according to  claim 7 , further comprising:
 a first insulating film that is provided between the first diffusion source layer and the first semiconductor region and does not include the impurity or includes the impurity at a concentration less than the first diffusion source layer; and   a second insulating film that is provided between the second diffusion source layer and the first semiconductor region and does not include the impurity or includes the impurity at a concentration less than the second diffusion source layer.   
     
     
         10 . The semiconductor device according to  claim 7 , further comprising:
 a plurality of control gate electrodes that are provided above the plurality of first semiconductor regions, extend in a second direction different from the first direction, and are arranged in a direction intersecting the second direction;   a charge trapping layer that is provided at intersections of the plurality of first semiconductor regions and the plurality of control gate electrodes;   a first gate insulating film that is provided between the charge trapping layer and each of the plurality of first semiconductor regions; and   a second gate insulating film that is provided between the charge trapping layer and each of the plurality of control gate electrodes.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein the element separation regions are higher than an interface between the first gate insulating film and the charge trapping layer, extend from a position lower than an upper surface of the charge trapping layer to at least the second impurity diffusion layer in the first direction.   
     
     
         12 . A method of manufacturing a semiconductor device comprising:
 forming a plurality of mask layers that extend in a first direction and are arranged in a direction intersecting the first direction on a stacked body including a semiconductor layer of a first conduction type, a first gate insulating film provided on the semiconductor layer, and a charge trapping layer provided on the first gate insulating film;   performing a first etching process to a portion of the stacked body exposed from the plurality of mask layers to form a plurality of first trenches which extend in the first direction in the semiconductor layer and to form each first semiconductor region interposed between the plurality of first trenches;   forming a first insulating layer on a side surface of the first semiconductor region interposed between the plurality of first trenches, a side surface of the first gate insulating film, and a side surface of the charge trapping layer;   performing a second etching process to the semiconductor layer below the bottom of each of the plurality of first trenches to lower the bottom of each of the plurality of first trenches, to form a second trench; and   forming a second insulating layer in each of the plurality of first and second trenches to form an element separation region including the first insulating layer and the second insulating layer in each of the plurality of first and second trenches.   
     
     
         13 . The method of manufacturing the semiconductor device according to  claim 12 , further comprising:
 introducing, after the second trenches are formed, an impurity element of a second conduction type from a portion of the bottom of each of the plurality of second trenches and the side surface of each of the plurality of second trenches which is connected to the semiconductor layer to form a second semiconductor region of the second conduction type between the portion of the bottom and the side surface of each of the plurality of second trenches and the first semiconductor region.   
     
     
         14 . The method of manufacturing the semiconductor device according to  claim 13 ,
 wherein the second semiconductor region of the second conduction type is formed by introducing an impurity element of the second conduction type to the semiconductor layer using ion implantation   
     
     
         15 . The method of manufacturing the semiconductor device according to  claim 13 ,
 wherein, in the formation of the second insulating layer, the second insulating layer including the impurity element of the second conduction type is formed in each of the plurality of second trenches, and   the impurity element of the second conduction type is diffused from the second insulating layer to the semiconductor layer.   
     
     
         16 . A method of manufacturing a semiconductor device, comprising:
 forming a trench in a semiconductor substrate;   forming a first insulating film so as to cover an inner surface of the trench;   forming a first diffusion source layer, which is an insulating film including an impurity of a predetermined conduction type at a first concentration, in the trench covered with the first insulating film;   performing etching to the first insulating film and the first diffusion source layer such that the first diffusion source layer remains in a region with a first depth;   embedding a second insulating film which does not include the impurity or includes the impurity at a concentration less than the first diffusion source layer to a second depth in the trench in which the first insulating film and the first diffusion source layer have been formed;   forming a third insulating film so as to cover the inner surface of the trench in which the second insulating film has been formed;   forming a second diffusion source layer, which is an insulating film including an impurity of a predetermined conduction type at a second concentration, in the trench covered with the third insulating film;   performing etching to the third insulating film and the second diffusion source layer such that the second diffusion source layer with a predetermined thickness from a second depth remains in the trench; and   embedding a fourth insulating film which does not include the impurity or includes the impurity at a concentration less than the second diffusion source layer in the trench in which the third insulating film and the second diffusion source layer have been formed.   
     
     
         17 . The method of manufacturing the semiconductor device according to  claim 16 , further comprising:
 performing, after the fourth insulating film is embedded, a heat treatment.   
     
     
         18 . The method of manufacturing the semiconductor device according to  claim 16 ,
 wherein, in the formation of the trench, after a first gate insulating film and a charge trapping layer are formed on the semiconductor substrate, the trench which extends from an upper surface of the charge trapping layer to the semiconductor substrate in a first direction and is arranged in a second direction intersecting the first direction is formed, and   in the etching to the third insulating film and the second diffusion source layer, the etching is performed until the height of an upper surface of the second diffusion source layer is substantially equal to that of a surface of the semiconductor substrate.   
     
     
         19 . The method of manufacturing the semiconductor device according to  claim 18 ,
 wherein, in the embedding of the fourth insulating film, the fourth insulating film is embedded in the trench such that an upper surface of the fourth insulating film is higher than an interface between the first gate insulating film and the charge trapping layer,   the method further comprising:
 forming, after the fourth insulating film is embedded, a second gate insulating film so as to cover the charge trapping layer and the inner surface of the trench in which the fourth insulating film is formed; 
 forming a control gate electrode on the second gate insulating film; and 
 processing a region from the control gate electrode to the charge trapping layer such that the control gate electrode extends in the second direction and is arranged in the first direction.