Multilayer wiring board for an electronic device

Abstract

To provide a multilayer wiring board mainly used for an electronic device, in which a bump passing through an interlayer insulating film allows for interlayer connection between plural wiring films insulated from one another with plural interlayer insulating layers. In the multilayer wiring board, a circuit element such as an electronic part, a semiconductor chip, or a passive element is accommodated in the interlayer insulating films so as to connect its terminal with the corresponding wiring film. In particular, the semiconductor chip is polished to a thickness of 50 μm or smaller, and the multilayer wiring board itself for the electronic device has the flexibility.

1 . A method of manufacturing a multilayer wiring board for an electronic device, comprising:
 preparing a first metal plate by forming a first wiring film on a surface of a terminal bump formation metal layer;   preparing a semiconductor chip that is formed with a thickness of 50 μm or smaller;   preparing a second metal plate in which an interlayer connection bump for connection to the wiring film on the first metal plate and a semiconductor chip accommodating space for accommodating the semiconductor chip are formed on one surface of a wiring film formation metal layer, and the interlayer connection bump extends away from the one surface of the wiring film formation metal layer, and an interlayer insulating film is laminated thereon outside the semiconductor chip accommodating space;   subjecting the semiconductor chip to flip-chip bonding to one surface of the first metal plate on a side where the wiring film is formed such that its electrode is connected with the wiring film;   laminating the second metal plate through the interlayer insulating film on the one surface of the first metal plate on the side where the wiring film is formed by connecting to the wiring film formation metal layer on the second metal plate a top surface of the interlayer connection bump exposed to the interlayer insulating film while the semiconductor chip is accommodated within the semiconductor chip accommodating space;   forming a second wiring film by selectively etching the wiring film formation metal layer of the second metal plate; and   forming a third metal layer electrically interconnected with the first metal layer through a second interlayer insulating layer, including forming a capacitor on a surface of the third metal layer constituting a first electrode thereof, by forming a capacitor dielectric layer on the third metal layer and forming a second electrode on a surface of the capacitor dielectric layer.