Level shift circuit

Abstract

A level shift circuit includes a first input terminal, a second input terminal, a first output terminal, a second output terminal, a latch-type level shifter, a first current source and a second current source. The first input terminal receives an input signal; the second input terminal receives an inverse signal of the input signal; the first output terminal outputs an output signal; and the second output terminal outputs an inverse signal of the output signal. The latch-type level shifter is connected to the first input terminal, the second input terminal, the first output terminal and the second output terminal. The first current source is connected between a first high voltage input terminal of the latch-type level shifter and a voltage source. The second current source is connected between a second high voltage input terminal of the latch-type level shifter and the voltage source.

What is claimed is: 
     
         1 . A level shift circuit, comprising:
 a first input terminal configured to receive an input signal;   a second input terminal configured to receive an inverse signal of the input signal;   a first output terminal configured to output an output signal;   a second output terminal configured to receive an inverse signal of the output signal;   a latch-type level shifter electrically connected to the first input terminal, the second input terminal, the first output terminal, and the second output terminal;   a first current source electrically connected between a first high voltage input terminal of the latch-type level shifter and a voltage source; and   a second current source electrically connected between a second high voltage input terminal of the latch-type level shifter and the voltage source.   
     
     
         2 . The level shift circuit of  claim 1 , wherein the first current source comprises a P-type transistor having a gate connected to a first bias voltage, a source connected to the voltage source, and a drain connected to the latch-type level shifter. 
     
     
         3 . The level shift circuit of  claim 1 , wherein the second current source comprises a P-type transistor having a gate connected to a second bias voltage, a source connected to the voltage source, and a drain connected to the latch-type level shifter. 
     
     
         4 . The level shift circuit of  claim 1 , wherein the first current source comprises a P-type transistor having a gate connected to a first bias voltage, a source connected to the voltage source, and a drain connected to the latch-type level shifter; and the second current source comprises a P-type transistor having a gate connected to a second bias voltage, a source connected to the voltage source, and a drain connected to the latch-type level shifter. 
     
     
         5 . The level shift circuit of  claim 1 , being disposed in a driving circuit of an LCD panel. 
     
     
         6 . A level shift circuit, comprising:
 a first transistor having a gate configured to receive an input signal, a drain configured to output an output signal, and a source connected to a low voltage terminal;   a second transistor having a gate configured to receive an inverse signal of the input signal, a drain configured to output an inverse signal of the output signal, and a source connected to the low voltage terminal,   a third transistor having a gate connected to the drain of the second transistor and a drain connected to the drain of the first transistor;   a fourth transistor having a gate connected to the drain of the first transistor and a drain connected to the drain of the second transistor;   a fifth transistor having a gate configured to receive a first bias voltage, a drain connected to a source of the third transistor, and a source connected to a high voltage terminal; and   a sixth transistor having a gate configured to receive a second bias voltage, a drain connected to a source of the fourth transistor, and a source connected to the high voltage terminal;   wherein the first transistor and the second transistor are N-type transistors;   wherein the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are P-type transistors.   
     
     
         7 . The level shift circuit of  claim 6 , being disposed in a driving circuit of an LCD panel. 
     
     
         8 . A level shift circuit, comprising:
 a first transistor having a gate configured to receive an input signal, a drain configured to output an output signal, and a source connected to a high voltage terminal;   a second transistor having a gate configured to receive an inverse signal of the input signal, a drain configured to output an inverse signal of the output signal, and a source connected to the high voltage terminal;   a third transistor having a gate connected to the drain of the second transistor and a drain connected to the drain of the first transistor;   a fourth transistor having a gate connected to the drain of the first transistor and a drain connected to the drain of the second transistor;   a fifth transistor having a gate configured to receive a first bias voltage, a drain connected to a source of the third transistor, and a source connected to a low voltage terminal; and   a sixth transistor having a gate configured to receive a second bias voltage, a drain connected to a source of the fourth transistor, and a source connected to the low voltage terminal;   wherein the first transistor and the second transistor are P-type transistors;   wherein the third transistor, the fourth transistor, the fifth transistor and the sixth transistor are N-type transistors.   
     
     
         9 . The level shift circuit of  claim 8 , being disposed in a driving circuit of an LCD panel.