Semiconductor device and method for manufacturing same

Abstract

A device and a method for manufacturing the same in which with device includes a single crystal semiconductor substrate and an SOI substrate separated from the single crystal semiconductor substrate by a thin buried insulating film and having a thin single crystal semiconductor thin film (SOI layer), in which well diffusion layer regions, drain regions, gate insulating films, and gate electrodes of the SOI-type MISFET and the bulk-type MISFET are formed in the same steps. The bulk-type MISFET and the SOI-type MISFET are formed on the same substrate, so that board area is reduced and a simple process can be realized by making manufacturing steps of the SOI-type MISFET and the bulk-type MISFET common.

1 - 6 . (canceled) 
     
     
         7 . A semiconductor device including a MISFET, comprising:
 a semiconductor substrate including a first region and a second region;   an insulating layer formed over the first region of the semiconductor substrate;   a semiconductor layer formed over the insulating layer;   a gate insulating film of the MISFET formed over the semiconductor layer;   a gate electrode of the MISFET formed over the gate insulating film;   a source region and a drain region formed in the semiconductor layer;   a first silicon layer formed over the source region;   a second silicon layer formed over the drain region; and   an impurity region formed in the first region of the semiconductor substrate and formed under the MISFET,   wherein, in the second region, the insulating layer and the semiconductor layer are removed,   wherein the impurity region is also formed in the second region of the semiconductor substrate such that the impurity region is exposed from the insulating layer and the semiconductor layer,   wherein a third silicon layer is formed over the impurity region of the second region, and   wherein the gate electrode and the impurity region are electrically connected with each other via the third silicon layer.   
     
     
         8 . The semiconductor device according to the  claim 7 ,
 wherein an upper surface of the third silicon layer is higher than a bottom of the gate electrode.   
     
     
         9 . The semiconductor device according to the  claim 8 ,
 wherein the third silicon layer is directly connected to the gate electrode.   
     
     
         10 . The semiconductor device according to the  claim 7 ,
 wherein the first region and the second region are separated by an element isolation film, and   wherein the semiconductor layer and the third silicon layer are separated by the element isolation film.   
     
     
         11 . The semiconductor device according to the  claim 7 ,
 wherein silicide layers are formed on the gate electrode, the first silicon film, the second silicon film, and the third silicon film.   
     
     
         12 . The semiconductor device according to the  claim 7 ,
 wherein each of the source region, the drain region, and the impurity region includes an N type impurity.   
     
     
         13 . The semiconductor device according to the  claim 7 ,
 wherein the first, second, and third silicon layers are formed by an epitaxial method.   
     
     
         14 . The semiconductor device according to the  claim 7 ,
 wherein each thickness of the first, second, and third silicon layers is larger than a thickness of the gate electrode.