Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit includes a first register configured to store a first value indicating whether or not a macro is in a state at a first time point, and to update the first value to a second value indicating whether or not the macro is in the state at a second time point after the first time point, and a second register configured to store and retain the first value, and not to update the first value to the second value.

What is claimed is: 
     
         1 . A semiconductor integrated circuit comprising:
 a first register configured to store a first value indicating whether or not a macro is in a state at a first time point, and to update the first value to a second value indicating whether or not the macro is in the state at a second time point after the first time point; and   a second register configured to store and retain the first value, and not to update the first value to the second value.   
     
     
         2 . The semiconductor integrated circuit according to  claim 1 , wherein the state comprises a reset state. 
     
     
         3 . The semiconductor integrated circuit according to  claim 1 , wherein both the second value in the first register and the first value in the second register are output to a debugger coupled to the semiconductor integrated circuit. 
     
     
         4 . The semiconductor integrated circuit according to  claim 3 , wherein the first value in the second register is updated by the debugger. 
     
     
         5 . The semiconductor integrated circuit according to  claim 1 , wherein the first and second registers are coupled to a plurality of reset signals. 
     
     
         6 . The semiconductor integrated circuit according to  claim 1 , wherein said state comprises a reset state, and said macro becomes said reset state in response to receiving a reset signal. 
     
     
         7 . The semiconductor integrated circuit according to  claim 1 , wherein said first and second registers store said first and second values, respectively, when said macro is debugged. 
     
     
         8 . The semiconductor integrated circuit according to  claim 1 , further comprising: a control circuit that outputs said first and second values from said first and second registers to an external device. 
     
     
         9 . The semiconductor integrated circuit according to  claim 8 , wherein said control circuit outputs said first and second values to said external device in response to an instruction from said external device. 
     
     
         10 . The semiconductor integrated circuit according to  claim 8 , wherein said external device comprises a debugger performing a debug of said macro. 
     
     
         11 . The semiconductor integrated circuit according to  claim 8 , wherein said control circuit comprises a TAP controller to have a capture DR state in which said control circuit outputs said first and second values to said external device and to have an update DR state in which said control circuit stores said second value in said second register. 
     
     
         12 . The semiconductor integrated circuit according to  claim 11 , wherein said control circuit becomes said update DR state after said capture DR state, and
 wherein said control circuit stores in said second register said second value indicating that said macro has been in said predetermined state, responsively to becoming said update DR state, in case that said predetermined state of said macro is changed to another state between said capture DR state and said update DR state.   
     
     
         13 . A circuit comprising:
 a first register configured to store a first value indicating whether or not a macro is in a state at a first time point, and to update the first value to a second value indicating whether or not the macro is in the state at a second time point after the first time point; and   a second register configured to store and retain the first value, and not to update the first value to the second value.   
     
     
         14 . The circuit according to  claim 13 , wherein the state comprises a reset state. 
     
     
         15 . The circuit according to  claim 13 , wherein both the second value in the first register and the first value in the second register are output to a debugger coupled to the circuit. 
     
     
         16 . The circuit according to  claim 15 , wherein the first value in the second register is updated by the debugger. 
     
     
         17 . The circuit according to  claim 13 , wherein the first and second registers are coupled to a plurality of reset signals. 
     
     
         18 . A semiconductor integrated circuit comprising:
 a first storage configured to store a first value indicating whether or not a macro is in a state at a first time point, and to update the first value to a second value indicating whether or not the macro is in the state at a second time point after the first time point; and   a second storage configured to store and retain the first value.   
     
     
         19 . The circuit according to  claim 18 , wherein the second storage stores and retains the first value and does not update the first value to the second value. 
     
     
         20 . The circuit according to  claim 18 , wherein the state comprises a reset state and wherein both the second value in the first storage and the first value in the second storage are output to a debugger coupled to the circuit, and
 wherein the first value in the second storage is updated by the debugger and wherein the first and second storages are coupled to a plurality of reset signals.