Method of fabricating semiconductor package

Abstract

A stacked semiconductor package having a unit package, cover substrates, adhesive members and connection electrodes is presented. The unit package includes a substrate, a first circuit pattern and a second circuit pattern. The first circuit pattern is disposed over an upper face of the substrate. The second circuit pattern is disposed over a lower face of the substrate. The lower and upper faces of the substrate oppose each other. The first and second semiconductor chips are respectively electrically connected to the first and second circuit patterns. The cover substrates are opposed to the first semiconductor chip and the second semiconductor chip. The adhesive members are respectively interposed between the unit package and the cover substrates. The connection electrodes pass through the unit package, the cover substrates and the adhesive members and are electrically connected to the first and second circuit patterns.

What is claimed is: 
     
         1 . A method for fabricating a semiconductor package, comprising the steps of:
 providing a mother substrate having circuit patterns formed thereon;   attaching semiconductor chips on the mother substrate so that the semiconductor chips are electrically coupled to the respective circuit patterns;   disposing adhesive members over the mother substrate to cover semiconductor chips and to fill in spaces between the circuit patterns and the semiconductor chips;   covering the adhesive members with cover substrates over the mother substrate; and   forming a connection electrode passing through the mother substrate, the first and second circuit patterns, adhesive members, and the cover substrates to electrically connect the first and second circuit patterns together.   
     
     
         2 . The method according to  claim 1 , wherein the mother substrate comprises:
 a first face;   a second face facing away the first face,   first and second chip groups disposed on the respective first and second faces of the mother substrate; and   first and second chip regions disposed in the respective first and second chip groups, wherein the circuit patterns formed in the respective first and second chip regions.   
     
     
         3 . The method according to  claim 2 , wherein the circuit patterns comprise:
 first circuit patterns formed in the respective first chip regions; and   second circuit patterns formed in the respective second chip regions.   
     
     
         4 . The method according to  claim 1 , wherein the semiconductor chips and the circuit patterns are electrically connected to a bumps formed in the semiconductor chips. 
     
     
         5 . The method according to  claim 1 , wherein the semiconductor chips and the circuit patterns are electrically connected to a conductive wires. 
     
     
         6 . The method according to  claim 1 , wherein at least two mother substrates are stacked on each other. 
     
     
         7 . The method according to  claim 2 , wherein the first and second chip groups are formed over the mother substrate in a matrix shape, and the first and second chip groups are formed at substantially the same position in the mother substrate on the respective first and second face. 
     
     
         8 . The method according to  claim 1 , further comprising the step of: electrically connecting a connection member to the connection electrode exposed from one of the cover substrates after the step of forming the connection electrode. 
     
     
         9 . The method according to  claim 8 , further comprising the step of: forming a wiring over the cover substrate to electrically connect together the connection electrode to the connection member. 
     
     
         10 . The method according to  claim 1 , further comprising the step of: applying heat and pressure to the adhesive members, wherein the step of applying is performed after the step of covering the adhesive members with cover substrates. 
     
     
         11 . The method according to  claim 1 , further comprising the steps of:
 forming third circuit patterns aligned with the circuit patterns over one face of the at least one cover substrate;   mounting a third semiconductor chip onto the third circuit pattern; and   connecting the third circuit pattern to the connection electrode during the step of forming the connection electrode, wherein the steps of forming and mounting are performed before the step of covering the adhesive members with cover substrates.   
     
     
         12 . The method according to  claim 2 , further comprising the steps of:
 inspecting the mother substrate to diagnose whether any circuit patterns formed in any respective first or second chip region is faulty;   removing a portion of the mother substrate to form an opening in the mother substrate that corresponds to any first or second chip region that has a respective first or second circuit pattern which is diagnosed to be faulty; and   disposing a good substrate into the opening of the mother substrate,   wherein the steps of inspecting, removing and disposing are performed after the step of providing the mother substrate, and before the step of attaching semiconductor chips on the mother substrate.   
     
     
         13 . The method according to  claim 2 , further comprising the steps of:
 inspecting the mother substrate to diagnose whether any circuit patterns formed in any respective first or second chip group is faulty;   removing a portion of the mother substrate to form an opening in the mother substrate corresponding to any first or second chip group that has a respective first or second circuit pattern which is diagnosed to be faulty ; and   disposing a good substrate into the opening of the mother substrate,   wherein the steps of inspecting, removing and disposing are performed after the step of providing the mother substrate, and before the step of attaching semiconductor chips on the mother substrate.   
     
     
         14 . A method for fabricating a semiconductor package, comprising the steps of:
 disposing a substrate, in which semiconductor chips are mounted on circuit patterns respectively disposed in a plurality of chip regions, into a plurality of openings formed in a mother substrate;   disposing adhesive members over the mother substrate to cover the respective semiconductor chips;   covering the adhesive member with a cover substrate over the mother substrate   forming a connection electrode passing through the cover substrate, the first and second circuit patterns, adhesive members, and the mother substrate and electrically connected with the circuit pattern.   
     
     
         15 . The method according to  claim 14 , wherein the circuit pattern and the semiconductor chip are electrically connected together with a conductive wire. 
     
     
         16 . The method according to  claim 14 , wherein at least two mother substrates are stacked on each other. 
     
     
         17 . The method according to  claim 14 , further comprising the step of:
 applying heat and pressure to the adhesive member wherein the applying heat and pressure step is performed after the step of covering the adhesive member with a cover substrate.   
     
     
         18 . The method according to  claim 12 , wherein the good substrate comprises a good first and second circuit patterns. 
     
     
         19 . The method according to  claim 13 , wherein the good substrate comprises a good first and second circuit patterns.