US2013234323A1PendingUtilityA1
Semiconductor chip and manufacturing method thereof
Est. expiryMar 8, 2032(~5.6 yrs left)· nominal 20-yr term from priority
Inventors:Toru Miyazaki
H10W 90/736H10W 90/724H10W 90/722H10W 90/297H10W 90/00H10W 74/121H10W 74/117H10W 72/9415H10W 72/07236H10W 72/01271H10W 72/01257H10W 72/01235H10W 72/952H10W 72/944H10W 72/942H10W 72/877H10W 72/252H10W 72/248H10W 72/222H10W 72/221H10W 72/0198H10W 72/29H10W 72/20H10W 72/072H01L 24/11H01L 24/12
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Claims
Abstract
A semiconductor device comprising stacked substrates through a bump, the bump comprising a solder bump formed on a copper bump wherein the solder bump includes Zn.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A semiconductor device comprising:
a first substrate; and a second substrate stacked on the first substrate through a bump, the bump comprising a solder bump formed on a copper bump formed over the second substrate; wherein the solder bump includes Zn.
2 . The semiconductor device according to claim 1 , further comprising;
a through-electrode penetrating the second substrate, the bump being electrically connected with the through-electrode.
3 . The semiconductor device according to claim 1 ,
wherein a concentration of Zn in an upper portion of the solder bump is lower than a concentration of Zn in a lower portion of the solder bump, the lower portion of the solder bump is in contact with the copper bump.
4 . The semiconductor device according to claim 1 ;
wherein the solder bump includes 1 to 5% by weight of Zn.
5 . The semiconductor device according to claim 1 ;
wherein the solder bump further includes Bi
6 . The semiconductor device according to claim 2 ;
wherein the solder bump further includes Bi.
7 . The semiconductor device according to claim 1 ;
wherein the solder bump further includes Cu.
8 . The semiconductor device according to claim 2 ;
wherein the solder hump further includes Cu.
9 . The semiconductor device according to claim 4 ;
wherein the solde bump further includes Cu.
10 . A method of manufacturing a semiconductor device, the semiconductor device comprising a first substrate stacked on a second substrates through a bump, the bump comprising a solder bump formed on a copper hump formed over the first substrate, the method comprising:
forming the copper bump over the first substrate; forming a Sn/Zn alloy layer on the copper bump; forming a Sn/Ag alloy layer on the Sn/Zn alloy; and heating and reflowing the Sn/Zn alloy layer and the Sn/Ag alloy layer.
11 . The method according to claim 10 ;
wherein the first substrate has a through-electrode penetrating the first substrate, and the bump is electrically connected with the through-electrode.
12 . The method according to claim 10 ;
wherein the Sn/Zn alloy includes 1 to 5% by weight of Zn.
13 . The method according to claim 10 ;
wherein the Sn/Zn alloy layer and/or the Sn/Ag alloy layer further includes Bi.
14 . The method according to claim 11 ;
wherein the Sn/Zn alloy layer and/or the Sn/Ag alloy layer further includes Bi.
15 . The method according to claim 12 ;
wherein the Sn/Zn alloy layer and/or the Sn/Ag alloy layer further includes Bi.
16 . The method according to claim 10 ;
wherein the Sn/Zn alloy layer and/or the Sn/Ag alloy layer further includes Cu.
17 . The method according to claim 11 ;
wherein the Sn/Zn alloy layer and/or the Sn/Ag alloy layer further includes Cu.
18 . The method according to claim 12 ;
wherein the Sn/Zn alloy layer and/or the Sn/Ag alloy layer further includes Cu.Join the waitlist — get patent alerts
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