Interconnect structure for improved time dependent dielectric breakdown

Abstract

The present disclosure provides a method of forming an interconnect to an electrical device. In one embodiment, the method of forming an interconnect includes providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact that is in electrical communication with the at least one electrical device. An interconnect metal layer is formed on the device layer, and a tantalum-containing etch mask is formed on a portion of the interconnect metal layer. The interconnect metal layer is etched to provide a trapezoid shaped interconnect in communication with the at least one electrical device. The trapezoid shaped interconnect has a first surface that is in contact with the device layer with a greater width than a second surface of the trapezoid shaped interconnect that is in contact with the tantalum-containing etch mask.

What is claimed is: 
     
         1 . A method of forming an interconnect comprising:
 providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electrical device, and a contact in electrical communication with the at least one electrical device;   forming an metal seed layer on the device layer;   forming an interlevel dielectric layer on the metal seed layer;   etching a trapezoid shaped via in the interlevel dielectric layer exposing a first portion of the metal seed layer, wherein a first width of a first opening of the trapezoid shaped via at an interface between the interlevel dielectric layer and the metal seed layer is greater than a second width of a second opening of the trapezoid shaped via at a surface of the interlevel dielectric layer that is opposite the interface of the interlevel dielectric layer and the metal seed layer; and   filling the trapezoid shaped via with an interconnect metal to provide a trapezoid shaped interconnect in electrical communication with the contact to the at least one electrical device.   
     
     
         2 . The method of  claim 1 , wherein the metal seed layer is blanket deposited across an entire width of the device layer. 
     
     
         3 . The method of  claim 1 , wherein the interlevel dielectric layer is composed of a carbon based low k dielectric, and the etching of the trapezoid shaped via in the interlevel dielectric layer to expose the first portion of the metal seed layer comprises a chemistry comprised of CF 4 , Ar, CHF 3 , N 2 , O 2  or a combination thereof. 
     
     
         4 . The method of  claim 3 , wherein the filling of the trapezoid shaped via with the interconnect metal comprises depositing copper (Cu), gold (Au), cobalt (Co), nickel (Ni) or combinations thereof. 
     
     
         5 . The method of  claim 1 , wherein the at least one electrical device includes two electrical devices and following filling the trapezoid shaped via with the interconnect metal, the method further comprises:
 removing the interlevel dielectric layer;   etching the metal seed layer using the trapezoid shaped interconnect as an etch mask; and   forming a low-k dielectric layer separating the trapezoid shaped interconnect to the two electrical devices.   
     
     
         6 . A method of forming an interconnect comprising:
 providing a device layer on a substrate, wherein the device layer comprises at least one electrical device, an intralevel dielectric over the at least one electric device, and a contact in electrical communication with the at least one electrical device;   forming an low-k dielectric layer on the device layer;   etching a trapezoid shaped via in the low-k dielectric layer exposing a portion of device layer including the contact, wherein a first width of a first opening of the trapezoid shaped via at an interface between the low-k dielectric layer and the device layer is greater than a second width of a second opening of the trapezoid shaped via at a surface of the low-k dielectric layer that is opposite the interface of the low-k dielectric layer and device layer;   forming a metal seed layer on sidewalls of the trapezoid shaped via and an exposed portion of the device layer at the first opening of the trapezoid shaped via; and   filling the trapezoid shaped via with an interconnect metal to provide a trapezoid shaped interconnect that is in electrical communication with the contact to the at least one electrical device.   
     
     
         7 . The method of  claim 6 , wherein the low-k dielectric material is composed of a carbon based low k dielectric, and the etching of the trapezoid shaped via in the low-k dielectric layer comprises reactive ion etch having an etch chemistry that is composed of a chemistry comprising CF 4 , Ar, CHF 3 , N 2 , O 2  or a combination thereof. 
     
     
         8 . The method of  claim 6 , wherein the metal seed layer is a conformal layer. 
     
     
         9 . The method of  claim 8 , further comprising a conformal metal barrier layer that is present between the metal seed layer and the sidewalls of the trapezoid shaped via and the exposed portion of the device layer at the first opening of the trapezoid shaped via. 
     
     
         10 . An electrical structure comprising:
 a plurality of semiconductor devices having a workfunction ranging from −5.1 eV to 4.0 eV;   trapezoid shaped interconnects in electrical communication with each of the plurality of semiconductor devices, wherein the trapezoid shaped interconnects have a base width that is greater than a width of the trapezoid shaped interconnects upper surface, wherein adjacent trapezoid shaped interconnects are separated by a pitch ranging from 20 nm to 300 nm; and   a low-k dielectric material separating the adjacent trapezoid shaped interconnects.   
     
     
         11 . The electrical device of  claim 10 , wherein the semiconductor devices each include a gate structure, a source region and a drain region, wherein at least a portion of the source region and the drain region are present in the semiconductor substrate, and the gate structure is present on a surface of the semiconductor substrate. 
     
     
         12 . The electrical device of  claim 11 , wherein the semiconductor substrate is a semiconductor on insulator (SOI) substrate or a bulk semiconductor substrate. 
     
     
         13 . The electrical device of  claim 10 , wherein the semiconductor devices are p-type or n-type devices. 
     
     
         14 . The electrical device of  claim 10 , wherein the electrical structure further comprises memory devices. 
     
     
         15 . The electrical device of  claim 10 , wherein the trapezoid shaped interconnects comprise an interconnect metal layer and a barrier metal layer. 
     
     
         16 . The electrical device of  claim 15 , wherein the barrier metal layer is composed of a metal selected from the group consisting of tantalum, tantalum nitride and a combination thereof. 
     
     
         17 . The electrical device of  claim 15 , wherein the interconnect metal layer is composed of a metal that is selected from the group consisting of copper, tungsten, aluminum, molybdenum, ruthenium, gold, cobalt, nickel and combinations thereof. 
     
     
         18 . The electrical device of  claim 10 , wherein the trapezoid shaped interconnects have a base width ranging from 12 nm to 300 nm. 
     
     
         19 . The electrical device of  claim 10 , wherein the trapezoid shaped interconnects have an upper surface with a width ranging from 10 nm to 150 nm.