Integrated circuit and method for fabricating the same

Abstract

An integrated circuit includes a substrate, a first semiconductor device, a second semiconductor device and an interlayer dielectric layer. At least one isolation structure has been formed in the he substrate so as to separate the substrate into a first active region and a second active region. The first semiconductor device disposed on the first active region of the substrate includes a first gate insulating layer and a poly-silicon gate stacked on the substrate sequentially. The second semiconductor device disposed on the second active region of the substrate includes a second gate insulating layer and a metal gate stacked on the substrate sequentially. The material of the second gate insulating layer is different from that of the first gate insulating layer. The thickness of the metal gate is greater than that of the poly-silicon gate. The interlayer dielectric layer is disposed on the substrate and covering the first semiconductor device.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a substrate with at least one of isolation structures formed therein so as to separate the substrate into a first active region and a second active area;   a first semiconductor device disposed on the first active region of the substrate and comprising:
 a first gate insulating layer having a first dielectric constant disposed on the substrate the first gate insulating layer; and 
 a poly-silicon gate disposed on the first gate insulating layer; 
   a second semiconductor device disposed on the second active region of the substrate and comprising:
 a second gate insulating layer disposed on the substrate, wherein the material of the second gate insulating layer is different from that of the first gate insulating layer; 
 a metal gate having a second thickness disposed on the second gate insulating layer, wherein the second thickness is greater than the first thickness; and 
   an interlayer dielectric layer disposed on the substrate and covering the first semiconductor device.   
     
     
         2 . The integrated circuit according to  claim 1 , wherein the first gate insulating layer has a first dielectric constant and the second agate insulating layer has a second dielectric constant greater than the first dielectric constant. 
     
     
         3 . The integrated circuit according to  claim 1 , wherein the first semiconductor device further comprises a first spacer disposed on sidewalls of the poly-silicon gate, and the second semiconductor device further comprises a second spacer disposed on sidewalls of the metal gate. 
     
     
         4 . The integrated circuit according to  claim 3 , wherein the first semiconductor device further comprises a plurality of first source/drain regions disposed in the substrate beside the first spacer, the second semiconductor device further comprises a plurality of second source/drain disposed in the substrate beside the second spacer. 
     
     
         5 . The integrated circuit according to  claim 3 , further comprises a plurality of source/drain metal salicides disposed in the substrate and located on the first source/drain regions and the second source/drain regions. 
     
     
         6 . The integrated circuit according to  claim 1 , wherein the first semiconductor device further comprises a metal salicide pattern disposed on the poly-silicon gate. 
     
     
         7 . The integrated circuit according to  claim 1 , wherein the first gate insulating layer comprises at least one of oxide layer and nitride layer. 
     
     
         8 . A method for fabricating an integrated circuit, comprising the steps of:
 providing a substrate with at least one isolation structure formed therein so as to separate the substrate into a first active region with a first stacked structure formed thereon and a second active region with a second stacked structure formed thereon;   forming an interlayer dielectric layer covering the first stacked structure and the second stacked structure; and   planarizing the interlayer dielectric layer to expose the top surface of the first stacked structure,   wherein the second stacked structure is still covered by the interlayer dielectric layer after planarizing.   
     
     
         9 . The method for fabricating the integrated circuit according to  claim 8 , wherein the second stacked structure comprises a second gate insulating layer and a dummy gate sequentially formed on the substrate, and after planarizing the interlayer dielectric layer, the method further comprises the steps of:
 removing the dummy gate so as to form an opening; and   forming a metal gate in the opening.   
     
     
         10 . The method for fabricating the integrated circuit according to  claim 8 , wherein the method for forming the first stacked structure and the second stacked structure comprises the steps of:
 forming a second dielectric material layer on the substrate;   forming a first poly-silicon layer on the second dielectric material layer;   removing a portion of the second dielectric material layer and a portion of the first poly-silicon layer to expose the first active region;   forming a first dielectric material layer on the first active region;   forming a second poly-silicon layer conformally on the substrate, wherein the second poly-silicon layer has a first thickness and constructs a gate material layer with the first poly-silicon, a first portion of the gate material layer is the portion of the second poly-silicon layer located on the first active region and a second portion of the gate material layer is constructed from the portion of the first poly-silicon layer remained on the substrate and the portion of the second poly-silicon layer located on the second active region, the second portion of the gate material layer has a second thickness greater than the first thickness; and   patterning the gate material layer, the first dielectric material layer and the second dielectric material layer to form the first stacked structure on the first active region and the second stacked structure on the second active region, wherein the first stacked structure comprises a first gate insulating layer and a poly-silicon gate sequentially stacked on the substrate, and the second stacked structure comprises a second gate insulating layer and a dummy gate sequentially stacked on the substrate.   
     
     
         11 . The method for fabricating the integrated circuit according to  claim 10 , wherein the first dielectric material layer has a first dielectric constant and the second dielectric material layer has a second dielectric constant greater than the first dielectric constant. 
     
     
         12 . The method for fabricating the integrated circuit according to  claim 10 , further comprising the step of forming a mask layer on the gate material layer conformally before patterning the gate material layer, the first dielectric material layer and the second dielectric material layer, wherein the mask layer is patterned with the gate material layer, the first dielectric material layer and the second dielectric material layer. 
     
     
         13 . The method for fabricating the integrated circuit according to  claim 12 , wherein before forming the interlayer dielectric layer, further comprising the steps of:
 removing a portion of the mask layer to expose the poly-silicon gate; and   doping the poly-silicon gate.   
     
     
         14 . The method for fabricating the integrated circuit according to  claim 13 , further comprising the step of forming a plurality of first source/drain regions in the substrate beside the dummy gate and a plurality of second source/drain regions in the substrate beside the poly-silicon gate while doping the poly-silicon gate. 
     
     
         15 . The method for fabricating the integrated circuit according to  claim 14 , further comprising the step of forming a plurality of source/drain metal silicides in the substrate and on the first source/drain regions and the second source/drain regions. 
     
     
         16 . The method for fabricating the integrated circuit according to  claim 8 , wherein the method for forming the first stacked structure and the second stacked structure comprises the steps of:
 forming a first dielectric material layer and a gate material layer on the substrate sequentially, wherein the first dielectric material layer covers the first active region and the second active region, the gate material has a first portion with a first thickness located above the first active region and the second portion with a second thickness located above the second active region greater than the first thickness; and   patterning the gate material layer and the first dielectric material layer to form the first stacked structure on the first active region and the second stacked structure on the second active region, wherein the first stacked structure comprises a first gate insulating layer and a poly-silicon gate sequentially stacked on the substrate, and the second stacked structure comprises a patterning first dielectric material layer and a dummy gate sequentially stacked on the substrate.   
     
     
         17 . The method for fabricating the integrated circuit according to  claim 16 , wherein after planarizing the interlayer dielectric layer, the method further comprises the steps of:
 removing the dummy gate so as to form an opening exposing the patterning first dielectric material layer;   removing the patterning first dielectric material layer;   forming a second gate insulating layer in the opening; and   forming a metal gate in the opening.   
     
     
         18 . The method for fabricating the integrated circuit according to  claim 17 , wherein the first dielectric material layer has a first dielectric constant and the second gate insulating layer has a second dielectric constant greater than the first dielectric constant. 
     
     
         19 . The method for fabricating the integrated circuit according to  claim 18 , wherein the method of forming the gate material layer comprises the steps of:
 forming a poly-silicon layer with the second thickness on the first dielectric material layer; and   thinning a portion of the poly-silicon layer located on the first active region to the first thickness.   
     
     
         20 . The method for fabricating the integrated circuit according to  claim 8 , further comprises the step of forming a first spacer on the sidewalls of the first stacked structure and a second spacer on the sidewalls of the second stacked structure before forming the interlayer dielectric layer. 
     
     
         21 . The method for fabricating the integrated circuit according to  claim 20 , further comprises the step of forming a plurality of first source/drain regions in the substrate beside the first spacer and a plurality of second source/drain regions in the substrate beside the second spacer before forming the interlayer dielectric layer. 
     
     
         22 . The method for fabricating the integrated circuit according to  claim 8 , further comprising the step of forming a metal silicides pattern on the poly-silicon gate.