Methods and Apparatus for LDMOS Transistors

Abstract

An LDMOS transistor includes a gate including a conductive material over an insulator material, a source including a first impurity region and a second impurity region, a third impurity region, and a drain including a fourth impurity region and a fifth impurity region. The first impurity region is of a first type, and the second impurity region is of an opposite second type. The third impurity region extends from the source region under the gate and is of the first type. The fourth impurity region is of the second type, the fifth impurity region is of the second type, and the fourth impurity region impinges the third impurity region.

1 - 18 . (canceled) 
     
     
         19 . A transistor comprising:
 a gate including a conductive material over an insulator material;   a source including a p+ region and an n+ region, the p+ region being on a side of the n+ region farther from the gate;   a p-body abutting the p+ region and the n+ region and extending from the source region under the gate, the p-body implanted in an high-voltage (HV) n-well and has a drain-side edge aligned with a drain-side edge of the gate; and   a drain including an n-doped drain region and an n+ region surrounded by the n-doped drain region, the n+ region of the drain having a higher concentration than the n-doped drain region, the n-doped drain region impinging upon the p-body, is shallower than the p-body, and extends above a portion of the p-body.   
     
     
         20 . The transistor of claim  9 , wherein the p+ region and the n+ region of the source are within the p-body. 
     
     
         21 . The transistor of claim  10 , wherein the p-body is deeper than the p+ region and the n+ region. 
     
     
         22 . The transistor of claim  9 , wherein the n+ region of the drain is within the n-doped drain region. 
     
     
         23 . The transistor of claim  12 , wherein the n-doped drain region is deeper than the n+ region of the drain. 
     
     
         24 . The transistor of claim  9 , wherein the gate extends over a drain-side edge of the p-body. 
     
     
         25 . A transistor comprising:
 a gate including a conductive material over an insulator material;   a source including a p+ region and an n+ region, the p+ region being on a side of the n+ region farther from the gate;   a p-body abutting the p+ region and the n+ region and extending from the source region under the gate; and   a drain including an n-doped drain region and an n+ region surrounded by the n-doped drain region, the n-doped drain region impinging upon the p-body beneath the gate, is shallower than the p-body, and extends above a portion of the p-body.   
     
     
         26 . The transistor of claim  15 , wherein a drain side edge of the p-body aligns with a drain-side edge of the gate, and the n-doped drain region has a source-side edge that extends past the drain-side edge of the gate. 
     
     
         27 . The transistor of claim  15 , wherein the n+ region of the source has a portion that extends beneath the gate. 
     
     
         28 . The transistor of claim  15 , wherein the n+ region of the drain is within the n-doped drain region. 
     
     
         29 . The transistor of claim  15 , wherein the p-body is implanted in an high-voltage (HV) n-well.