Semiconductor package and fabrication method thereof

Abstract

A fabrication method of a semiconductor package includes the steps of: forming a release layer on a carrier having concave portions; disposing chips on the release layer in the concave portions of the carrier; forming an encapsulant on the chips and the release layer; forming a bonding layer on the encapsulant; removing the release layer and the carrier so as to expose the active surfaces of the chips; and forming a circuit structure on the encapsulant and the chips. Since the release layer is only slightly adhesive to the chips and the encapsulant, the present invention avoids warpage of the overall structure during a thermal cycle caused by incompatible CTEs.

What is claimed is: 
     
         1 . A semiconductor package, comprising:
 an encapsulant having a first surface formed with a protruding portion and a second surface opposite to the first surface;   a chip embedded in the protruding portion of the encapsulant, wherein the chip has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, the active surface and the electrode pads being exposed from the protruding portion of the encapsulant;   a circuit structure formed on the first surface of the encapsulant and the active surface of the chip and electrically connected to the electrode pads of the chip; and   a bonding layer formed on the second surface of the encapsulant.   
     
     
         2 . The package of  claim 1 , wherein the circuit structure has at least a dielectric layer formed on the encapsulant and the active surface of the chip, a circuit layer formed on the dielectric layer, and a plurality of conductive vias formed in the dielectric layer for electrically connecting the circuit layer and the electrode pads of the chip. 
     
     
         3 . The package of  claim 2 , further comprising an insulating protection layer formed on the outermost one of the at least a dielectric layer of the circuit structure and having a plurality of openings formed therein such that a portion of the circuit layer is exposed through the openings so as for conductive elements to be disposed thereon. 
     
     
         4 . The package of  claim 1 , wherein the circuit structure has at least a dielectric layer formed on the encapsulant, and a circuit layer formed on the dielectric layer and the active surface of the chip so as to electrically connect the electrode pads of the chip. 
     
     
         5 . The package of  claim 1 , wherein the bonding layer is made of polyimide (PI), a dry film or a semi-dry material. 
     
     
         6 . A fabrication method of a semiconductor package, comprising the steps of:
 providing a carrier having a plurality of concave portions on a surface thereof and a release layer formed on the surface having the concave portions;   disposing a plurality of chips on the release layer in the concave portions, respectively, wherein each of the chips has an active surface with a plurality of electrode pads and an inactive surface opposite to the active surface, the chips being disposed on the release layer via the active surfaces thereof;   forming an encapsulant on the chips and the release layer;   forming a bonding layer on the encapsulant;   removing the release layer and the carrier so as to expose the active surfaces of the chips; and   forming a circuit structure on the encapsulant and the active surfaces of the chips so as to electrically connect the circuit structure and the electrode pads of the chips.   
     
     
         7 . The method of  claim 6 , wherein the carrier is made of glass or metal. 
     
     
         8 . The method of  claim 6 , wherein the release layer is made of a hydrophobic material, an inorganic material or a high polymer. 
     
     
         9 . The method of  claim 6 , wherein the release layer is formed through plasma-enhanced chemical vapor deposition (PECVD). 
     
     
         10 . The method of  claim 6 , wherein the bonding layer is formed through lamination. 
     
     
         11 . The method of  claim 6 , wherein the bonding layer is made of polyimide (PI), a dry film or a semi-dry material. 
     
     
         12 . The method of  claim 6 , wherein the circuit structure has at least a dielectric layer formed on the encapsulant and the active surfaces of the chips, a circuit layer formed on the dielectric layer and a plurality of conductive vias formed in the dielectric layer for electrically connecting the circuit layer and the electrode pads of the chips. 
     
     
         13 . The method of  claim 12 , further comprising forming an insulating protection layer on the outermost one of the at least a dielectric layer of the circuit structure and forming a plurality of openings in the insulating protection layer such that a portion of the circuit layer is exposed through the openings so as for conductive elements to be disposed thereon. 
     
     
         14 . The method of  claim 6 , wherein the circuit structure has at least a dielectric layer formed on the encapsulant and a circuit layer formed on the dielectric layer and the active surfaces of the chips for electrically connecting the electrode pads of the chips. 
     
     
         15 . The method of  claim 6 , before removing the release layer and the carrier, further comprising forming an isolation layer on the bonding layer, wherein the isolation layer is disposed on a support plate so as to be sandwiched between the support plate and the bonding layer. 
     
     
         16 . The method of  claim 15 , before forming the bonding layer on the encapsulant, further comprising sandwiching the isolation layer between the support plate and the bonding layer. 
     
     
         17 . The method of  claim 15 , wherein the isolation layer is free from being adhered to the support plate and the bonding layer. 
     
     
         18 . The method of  claim 15 , wherein the isolation layer is patterned to form gaps therein and then the isolation layer is embedded in the bonding layer such that portions of the bonding layer are positioned in the gaps for bonding with the support plate. 
     
     
         19 . The method of  claim 18 , after forming the circuit structure, further comprising cutting the overall structure along cutting paths through the gaps so as to remove the isolation layer and the support plate, thereby obtaining a plurality of semiconductor packages. 
     
     
         20 . The method of  claim 15 , wherein the isolation layer is less in area than the bonding layer and the support plate such a portion of the bonding layer encapsulates edges of the isolation layer for the bonding layer to be bonded with edges of the support plate. 
     
     
         21 . The method of  claim 20 , after forming the circuit structure, further comprising singulating the chips and cutting along the edges of the isolation layer so as to remove the support plate and the isolation layer, thereby obtaining a plurality of semiconductor packages. 
     
     
         22 . The method of  claim 6 , further comprising performing a singulation process so as to obtain a plurality of semiconductor packages.