Semiconductor memory, memory system, and method of controlling the same

Abstract

Various embodiments of a semiconductor system, semiconductor memory, and a method of controlling the same are disclosed. In one exemplary embodiment, the semiconductor memory may include a first circuit area configured to perform an operation corresponding to a general operation command and a second circuit area configured to provide the general operation command to the first circuit area. The second circuit area may be configured to determine whether the semiconductor memory selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory.

What is claimed is: 
     
         1 . A memory system comprising:
 a memory controller configured to output an identification information store command, general operation commands comprising a first operation command and a second operation command, unique identification information, and target identification information; and   a plurality of semiconductor memories, each semiconductor memory being configured to store the unique identification information in response to the identification information store command and check whether the semiconductor memory is selected based on the unique identification information and the target identification information in response to the first operation command, and perform an operation corresponding to the first operation command depending on the check result,   wherein the first operation command uses some of all bits of an address signal related to the first operation command.   
     
     
         2 . The memory system according to  claim 1 , wherein the memory controller is configured to provide the identification information store command and the unique identification information to the semiconductor memory in an initialization interval of the semiconductor memory. 
     
     
         3 . The memory system according to  claim 1 , wherein the semiconductor memory comprises:
 a first circuit area configured to perform operations corresponding to the first operation command and the second operation command; and   a second circuit area configured to store the unique identification information, check whether the semiconductor memory is selected based on the unique identification information and the target identification information, and provide the first operation command to the first circuit area depending on the check result.   
     
     
         4 . The memory system according to  claim 3 , wherein the first circuit area comprises a peripheral circuit and memory area. 
     
     
         5 . The memory system according to  claim 3 , wherein the first circuit area is configured to directly receive the second operation command through a command channel. 
     
     
         6 . The memory system according to  claim 3 , wherein the second circuit area is configured to receive the unique identification information through a data channel and receive the target identification information through an address channel. 
     
     
         7 . The memory system according to  claim 3 , wherein the second circuit area comprises:
 a command decoder configured to generate a first strobe signal in response to the identification information store command, generate a second strobe signal in response to the first operation command, and decode the first operation command;   a first storage unit configured to store the unique identification information in response to the first strobe signal; a second storage unit configured to store the target identification information in response to the second strobe signal;   an identification information determination unit configured to select one bit of the target identification information in accordance with the unique identification information and output the selected bit as an identification information confirm signal; and   a command transfer control unit configured to provide the first operation command to the first circuit area in response to the identification information confirm signal.