Stacked non-volatile memory with silicon carbide-based amorphous silicon thin film transistors

Abstract

A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silicon film or silicon carbide film, depending on the carbon content. The dielectric stack is formed over the channel region layer. In one embodiment, the dielectric stack is an ONO structure. The control gate is formed over the dielectric stack. This structure is repeated vertically to form the stacked structure. In one embodiment, the carbon content of the channel region layer is reduced for each subsequently formed layer.

What is claimed is: 
     
         1 . A method for fabricating a stacked non-volatile thin film memory device, the method comprising:
 forming a plurality of thin film FinFET memory cell layers stacked vertically on a substrate, the method for forming each memory cell layer comprising:
 forming a pair of source/drain regions vertically over the substrate; 
 forming a channel region of amorphous silicon film vertically over the substrate and between the pair of vertical source/drain regions; 
 increasing a carbon content in the amorphous silicon film to form a carbon-rich silicon film; 
 forming a dielectric stack around the channel region; and 
 forming a control gate around the dielectric stack. 
   
     
     
         2 . The method of  claim 1 , wherein forming a channel region of amorphous silicon film comprises forming an amorphous silicon selected from the group consisting of hydrogenated a-Si, deteuritated a-Si and fluorinated a-Si. 
     
     
         3 . The method of  claim 1 , wherein increasing the carbon content of the amorphous silicon film comprises increasing the carbon content of the amorphous silicon film at a lesser percentage for each subsequently formed vertically stacked thin film FinFET memory cell layer. 
     
     
         4 . The method of  claim 1  wherein increasing the carbon content of the amorphous silicon film comprises increasing the carbon content of the amorphous silicon film such that the carbon-rich silicon film of a particular layer of the plurality of thin film FinFET memory cell layers has a greater carbon content than a carbon-rich silicon film of a higher layer of the plurality of thin film FinFET memory cell layers. 
     
     
         5 . The method of  claim 1 , wherein increasing the carbon content of the amorphous silicon film comprises increasing the carbon content of the amorphous silicon film to a level to form the carbon-rich silicon film as a a silicon carbide film. 
     
     
         6 . The method of  claim 1 , wherein increasing the carbon content of the amorphous silicon film comprises controlling a Si:C growth temperature. 
     
     
         7 . The method of  claim 1 , wherein forming a control gate around the dielectric stack comprises forming the control gate to have the same thickness over three sides of the dielectric stack adjacent the control gate. 
     
     
         8 . The method of  claim 1 , wherein forming a control gate around the dielectric stack comprises forming the control gate to have the same thickness over two opposing sides of the dielectric stack adjacent the control gate and to have a lesser thickness over a top side of the dielectric stack adjacent the control gate. 
     
     
         9 . The method of  claim 1 , wherein forming a dielectric stack around the channel region comprises forming an oxide-nitride-oxide dielectric stack around the channel region. 
     
     
         10 . The method of  claim 1 , wherein forming a dielectric stack around the channel region comprises forming the dielectric stack to have graded stoichiometry. 
     
     
         11 . The method of  claim 1 , further including forming an amorphous silicon cap layer between the carbon-rich silicon film and the dielectric stack. 
     
     
         12 . The method of  claim 1  and further including forming an oxide layer between each layer of thin film memory cells. 
     
     
         13 . A method for fabricating a stacked non-volatile thin film memory device, the method comprising:
 forming a plurality of thin film FinFET memory cell layers stacked vertically on a substrate, the method for forming each memory cell layer comprising:
 forming a pair of source/drain regions vertically over the substrate; 
 forming a channel region of amorphous silicon film vertically over the substrate and between the pair of vertical source/drain regions; 
 increasing a carbon content in the amorphous silicon film to form a carbon-rich silicon film; 
 forming an amorphous silicon cap layer over the amorphous silicon film after increasing its carbon content; 
 forming a dielectric stack around the amorphous silicon cap layer; and 
 forming a control gate around the dielectric stack. 
   
     
     
         14 . The method of  claim 13  wherein increasing the carbon content of the amorphous silicon film comprises increasing the carbon content of the amorphous silicon film such that the carbon-rich silicon film of a particular layer of the plurality of thin film FinFET memory cell layers has a greater carbon content than a carbon-rich silicon film of each higher layer of the plurality of thin film FinFET memory cell layers. 
     
     
         15 . The method of  claim 13 , wherein forming a control gate around the dielectric stack comprises forming the control gate over two opposing sides of the dielectric stack and over a top side of the dielectric stack. 
     
     
         16 . The method of  claim 15 , wherein forming the control gate around the dielectric stack further comprises forming the control gate to have the same thickness on both opposing sides and the top side of the dielectric stack. 
     
     
         17 . The method of  claim 15 , wherein forming the control gate around the dielectric stack further comprises forming the control gate to have a greater thickness on both opposing sides of the dielectric stack than on the top side of the dielectric stack. 
     
     
         18 . A method for fabricating a stacked non-volatile thin film memory device, the method comprising:
 forming a plurality of thin film FinFET memory cell layers stacked vertically on a substrate, the method for forming each memory cell layer comprising:
 forming a pair of source/drain regions vertically over the substrate; 
 forming a channel region of amorphous silicon film vertically over the substrate and between the pair of vertical source/drain regions; 
 increasing a carbon content in the amorphous silicon film to form a carbon-rich silicon film, wherein the carbon content of the carbon-rich silicon film is less than a carbon content of a carbon-rich silicon film of any lower layer of the plurality of thin film FinFET memory cell layers; 
 forming a dielectric stack around the channel region; and 
 forming a control gate around the dielectric stack. 
   
     
     
         19 . The method of  claim 18 , wherein forming a control gate around the dielectric stack comprises forming the control gate to have a structure selected from the group consisting of a double gate structure and a triple gate structure. 
     
     
         20 . The method of  claim 18 , further including forming an amorphous silicon cap layer between the carbon-rich silicon film and the dielectric stack.