Information processor, control device, and image forming apparatus

Abstract

Provided is an information processor including: an operation unit performing logical operation or arithmetical operation; an execution unit executing predetermined functions based on the operation results; a clock signal generating unit generating a first clock signal to be a reference; a clock signal multiplying unit performing a multiplication operation on the first clock signal to generate a second clock signal; a clock signal selection unit selecting one of the first or second clock signals and supplies the selected signal to the execution unit; a memory storing data for setting the execution unit to be in an executable state in a readable and writable non-volatile memory; and a setting unit setting the execution unit to be in an executable state by causing the clock signal selection unit to select the first clock signal when reset is released and reading the data from the memory to start writing the data.

What is claimed is: 
     
         1 . An information processor comprising:
 an operation unit that performs logical operation or arithmetical operation;   an execution unit that executes predetermined functions based on the operation results of the operation unit;   a clock signal generating unit that generates a first clock signal to be a reference;   a clock signal multiplying unit that performs a multiplication operation on the first clock signal to generate a second clock signal;   a clock signal selection unit that selects one of the first and second clock signals and supplies the selected signal to the execution unit;   a memory that stores data for setting the execution unit to be in an executable state in a readable and writable non-volatile memory which holds stored information even when power is not supplied; and   a setting unit that sets the execution unit to be in an executable state by causing the clock signal selection unit to select the first clock signal when reset is released due to power being turned on and reading the data from the memory to start writing the data in the execution unit.   
     
     
         2 . The information processor according to  claim 1 ,
 wherein the data stored in the memory are data written in the execution unit so as to initially set the executable state or data written in the execution unit so as to set the executable state by resuming the execution from when the execution is interrupted.   
     
     
         3 . The information processor according to the  claim 1 ,
 wherein the setting unit causes the clock signal selection unit to select the second clock signal at least at a time that comes after a predetermined time elapses from when the reset is released, after a signal that shows that the second clock signal is set to a preset value is received from the clock signal multiplying unit, or after the execution unit is set to be in an executable state.   
     
     
         4 . The information processor according to the  claim 2 ,
 wherein the setting unit causes the clock signal selection unit to select the second clock signal at least at a time that comes after a predetermined time elapses from when the reset is released, after a signal that shows that the second clock signal is set to a preset value is received from the clock signal multiplying unit, or after the execution unit is set to be in an executable state.   
     
     
         5 . The information processor according to  claim 1 ,
 wherein the execution unit sets a timing of the signal generated to execute the predetermined functions, in response to each of the first and second clock signals supplied.   
     
     
         6 . The information processor according to  claim 2 ,
 wherein the execution unit sets a timing of the signal generated to execute the predetermined functions, in response to each of the first and second clock signals supplied.   
     
     
         7 . The information processor according to  claim 3 ,
 wherein the execution unit sets a timing of the signal generated to execute the predetermined functions, in response to each of the first and second clock signals supplied.   
     
     
         8 . The information processor according to  claim 4 ,
 wherein the execution unit sets a timing of the signal generated to execute the predetermined functions, in response to each of the first and second clock signals supplied.   
     
     
         9 . The information processor according to  claim 1 ,
 wherein the non-volatile memory is one of MRAM, FeRAM, PRAM, and ReRAM.   
     
     
         10 . The information processor according to  claim 2 ,
 wherein the non-volatile memory is one of MRAM, FeRAM, PRAM, and ReRAM.   
     
     
         11 . The information processor according to  claim 3 ,
 wherein the non-volatile memory is one of MRAM, FeRAM, PRAM, and ReRAM.   
     
     
         12 . The information processor according to  claim 4 ,
 wherein the non-volatile memory is one of MRAM, FeRAM, PRAM, and ReRAM.   
     
     
         13 . The information processor according to  claim 5 ,
 wherein the non-volatile memory is one of MRAM, FeRAM, PRAM, and ReRAM.   
     
     
         14 . The information processor according to  claim 6 ,
 wherein the non-volatile memory is one of MRAM, FeRAM, PRAM, and ReRAM.   
     
     
         15 . The information processor according to  claim 7 ,
 wherein the non-volatile memory is one of MRAM, FeRAM, PRAM, and ReRAM.   
     
     
         16 . The information processor according to  claim 8 ,
 wherein the non-volatile memory is one of MRAM, FeRAM, PRAM, and ReRAM.   
     
     
         17 . A control device comprising:
 a clock signal multiplying unit that performs a multiplication operation on a first clock signal supplied from the outside to generate a second clock signal;   a clock signal selection unit that selects one of the first and second clock signals; and   an execution unit that executes predetermined functions by a process in which the first clock signal is supplied when reset is released due to power being turned on, data are read from a readable and writable non-volatile memory that holds stored information even when power is not supplied, and writing starts to set the execution unit to be in an executable state.   
     
     
         18 . The control device according to  claim 17 , further comprising:
 a memory that stores data for setting the execution unit to be in an executable state in the non-volatile memory; and   a setting unit that causes the clock signal selection unit to select the first clock signal when reset is released due to power being turned on, and reads the data from the memory to start writing the data in the execution unit.   
     
     
         19 . The control device according to  claim 17 ,
 wherein the non-volatile memory is one of MRAM, FeRAM, PRAM, ReRAM.   
     
     
         20 . An image forming apparatus comprising:
 an image forming portion that forms an image on a recording member; and   a control unit that includes an operation unit performing logical operation or arithmetical operation, an execution unit executing predetermined functions based on the operation results of the operation unit, a clock signal generating unit generating a first clock signal to be a reference, a clock signal multiplying unit generating a second clock signal by performing a multiplication operation on the first clock signal, a clock signal selection unit selecting one of the first and second clock signals and supplying the selected signal to the execution unit, a memory storing data for setting the execution unit to be in an executable state in a readable and writable non-volatile memory that is able to hold stored information even when power is not supplied, and a setting unit setting the execution unit to be in an executable state by causing the clock signal selection unit to select the first clock signal when reset is released due to power being turned on and reading the data from the memory to start writing the data in the execution unit, and controls the image forming portion.