Structure comprising a ruthenium metal material

Abstract

A method for forming a ruthenium metal layer comprises combining a ruthenium precursor with a measured amount of oxygen to form a ruthenium oxide layer. The ruthenium oxide is annealed in the presence of a hydrogen-rich gas to react the oxygen in the ruthenium oxide with hydrogen, which results in a ruthenium metal layer. By varying the oxygen flow rate during the formation of ruthenium oxide, a ruthenium metal layer having various degrees of smooth and rough textures can be formed.

1 . A semiconductor device comprising:
 first and second dielectric sidewalls; and   a smooth-surfaced ruthenium metal material adjacent the first and second dielectric sidewalls.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the smooth-surfaced ruthenium metal material defines at least one capacitor bottom plate. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the smooth-surfaced ruthenium metal material defines at least one gate of a transistor. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the at least one gate comprises at least one control gate. 
     
     
         5 . The semiconductor device of  claim 1 , further comprising first and second spacers on the first and second dielectric sidewalls. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the smooth-surfaced ruthenium metal material is on an oxide. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the oxide is a gate oxide. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the first and second dielectric sidewalls define an opening in a dielectric material, wherein the smooth-surfaced ruthenium metal material is formed at least partially within the opening. 
     
     
         9 . A semiconductor device, comprising:
 a dielectric material having an opening therein, the opening defined by sidewalls; and   a smooth-surfaced ruthenium metal material in contact with the sidewalls of the dielectric material.   
     
     
         10 . The semiconductor device of  claim 9 , wherein the smooth-surfaced ruthenium metal material is in contact with the sidewalls of the dielectric material and with a conductive material below the opening. 
     
     
         11 . The semiconductor device of  claim 9 , wherein an upper surface of the dielectric material is co-planar with an upper surface of the smooth-surfaced ruthenium metal material. 
     
     
         12 . The semiconductor device of  claim 9 , further comprising a cell dielectric material on the smooth-surfaced ruthenium metal material. 
     
     
         13 . The semiconductor device of  claim 12 , further comprising a capacitor top plate on the cell dielectric material. 
     
     
         14 . The semiconductor device of  claim 13 , further comprising another dielectric material on the capacitor top plate and filling a remainder of the opening. 
     
     
         15 . The semiconductor device of  claim 9 , wherein the smooth-surfaced ruthenium metal material comprises a capacitor bottom plate. 
     
     
         16 . A semiconductor device, comprising:
 a transistor gate stack on a semiconductor wafer, the transistor gate stack comprising a gate oxide, a ruthenium control gate on the gate oxide, and a capping material on the ruthenium control gate.   
     
     
         17 . The semiconductor device of  claim 16 , wherein the ruthenium control gate comprises smooth-surfaced ruthenium. 
     
     
         18 . The semiconductor device of  claim 16 , further comprising spacers on sidewalls of the transistor gate stack. 
     
     
         19 . The semiconductor device of  claim 16 , wherein the smooth-surfaced ruthenium control gate comprises a thickness of between about 150 Å and about 800 Å. 
     
     
         20 . The semiconductor device of  claim 16 , wherein the capping material comprises a thickness of between about 100 Å and about 500 Å.