Semiconductor memory, memory system, and method of controlling the same

Abstract

Various embodiments of a semiconductor system, semiconductor memory, and a method of controlling the same are disclosed. In one exemplary embodiment, the semiconductor memory may include a first circuit area configured to perform an operation corresponding to a general operation command and a second circuit area configured to provide the general operation command to the first circuit area. The second circuit area may be configured to determine whether the semiconductor memory selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory.

What is claimed is: 
     
         1 . A semiconductor memory comprising:
 a first circuit area configured to perform an operation corresponding to a general operation command; and   a second circuit area configured to provide the general operation command to the first circuit area,   wherein the second circuit area is configured to determine whether the semiconductor memory is selected to perform the operation based on unique identification information and target identification information allocated to the semiconductor memory.   
     
     
         2 . The semiconductor memory according to  claim 1 , wherein the first circuit area comprises a peripheral circuit and memory area. 
     
     
         3 . The semiconductor memory according to  claim 1 , wherein the second circuit area is configured to receive the unique identification information through a data channel and receive the target identification information through an address channel. 
     
     
         4 . The semiconductor memory according to  claim 1 , wherein the second circuit area comprises:
 a command decoder configured to generate a first strobe signal in response to an identification information store command, generate a second strobe signal in response to an identification information check command, and decode the general operation command;   a first storage unit configured to store the unique identification information in response to the first strobe signal;   a second storage unit configured to store the target identification information in response to the second strobe signal; an identification information determination unit configured to select one bit of the target identification information in accordance with the unique identification information, and output the selected bit as an identification information confirm signal; and   a command transfer control unit configured to provide the general operation command to the first circuit area in response to the identification information confirm signal.   
     
     
         5 . A semiconductor memory comprising:
 a first circuit area configured to perform an operation corresponding to an operation command; and   a second circuit area configured to use unique identification information and target identification information to check whether or not the semiconductor memory is selected for the operation and provide the operation command to the first circuit area depending on the check result,   wherein the operation command uses some of all bits of an address signal related to the operation command.   
     
     
         6 . The semiconductor memory according to  claim 5 , wherein the first circuit area comprises a peripheral circuit and memory area. 
     
     
         7 . The semiconductor memory according to  claim 5 , wherein the first circuit area is configured to directly receive a second operation command excluding the operation command through a command channel. 
     
     
         8 . The semiconductor memory according to  claim 5 , wherein the second circuit area is configured to receive the unique identification information through a data channel, and receive the target identification information through an address channel. 
     
     
         9 . The semiconductor memory according to  claim 5 , wherein the second circuit area comprises:
 a command decoder configured to generate a first strobe signal in response to an identification information store command, generate a second strobe signal in response to the first operation command, and decode the first operation command;   a first storage unit configured to store the unique identification information in response to the first strobe signal;   a second storage unit configured to store the target identification information in response to the second strobe signal; an identification information determination unit configured to select one bit of the target identification information in accordance with the unique identification information and output the selected bit as an identification information confirm signal; and   a command transfer control unit configured to provide the first operation command to the first circuit area in response to the identification information confirm signal.