Current sensing for flash

Abstract

Sense amplifiers and memory devices include a current source coupled to a bit line connection, a sensing transistor having a control gate coupled to the bit line connection, and a data latch coupled to a source/drain region of the sensing transistor. The sensing transistor has a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process utilized to form the sense amplifier and/or the current source comprises a transistor having a channel length greater than one and a half times the channel length of a conventional transistor of the semiconductor manufacturing process utilized to form the sense amplifier

What is claimed is: 
     
         1 . A sense amplifier comprising:
 a current source coupled to a bit line connection;   a sensing transistor having a control gate coupled to the bit line connection; and   a data latch coupled to a source/drain region of the sensing transistor;   wherein the sensing transistor has a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process utilized to form the sense amplifier.   
     
     
         2 . The sense amplifier of  claim 1 , further comprising an isolation transistor coupled between the current source and the bit line connection. 
     
     
         3 . The sense amplifier of  claim 2 , wherein the isolation transistor is coupled to operate as a cascade amplifier in conjunction with the sensing transistor. 
     
     
         4 . The sense amplifier of  claim 2 , wherein a control gate of the isolation transistor is coupled to an output of the sense amplifier. 
     
     
         5 . The sense amplifier of  claim 2 , wherein the isolation transistor has a channel length greater than one and a half times the channel length of a conventional transistor of the semiconductor manufacturing process utilized to form the sense amplifier. 
     
     
         6 . The sense amplifier of  claim 2 , wherein the isolation transistor comprises a transistor of a multiplexer through which the sense amplifier is coupled to a bit line. 
     
     
         7 . The sense amplifier of  claim 1 , wherein the sensing transistor comprises an NFET transistor and another source/drain region of the sensing transistor is coupled to a reference node. 
     
     
         8 . The sense amplifier of  claim 7 , wherein the reference node comprises a ground. 
     
     
         9 . The sense amplifier of  claim 7 , wherein the current source is adapted to source a selected current to the bit line connection. 
     
     
         10 . The sense amplifier of  claim 1 , wherein the sensing transistor comprises a PFET transistor and another source/drain region of the sensing transistor is coupled to a voltage supply node. 
     
     
         11 . The sense amplifier of  claim 10 , wherein the current source is adapted to sink a selected current from the bit line connection. 
     
     
         12 . The sense amplifier of  claim 1 , wherein the current source comprises a transistor having a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process utilized to form the sense amplifier. 
     
     
         13 . A memory device, comprising:
 a plurality of memory cells selectively coupled to a bit line; and   a sense amplifier selectively coupled to the bit line, the sense amplifier comprising:
 a current source coupled to a bit line connection selectively coupled to the bit line; 
 a sensing transistor having a control gate coupled to the bit line connection; and 
 a data latch coupled to a source/drain region of the sensing transistor; 
 wherein the sensing transistor has a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process utilized to form the sense amplifier. 
   
     
     
         14 . A sense amplifier comprising:
 a current source coupled to a bit line connection;   a sensing transistor having a control gate coupled to the bit line connection;   a data latch coupled to a source/drain region of the sensing transistor;   wherein the current source comprises a transistor having a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process utilized to form the sense amplifier.   
     
     
         15 . The sense amplifier of  claim 14 , wherein the current source is adapted to either sink a selected current from the bit line connection or to source a selected current to the bit line connection. 
     
     
         16 . The sense amplifier of  claim 14 , wherein the sensing transistor comprises an NFET transistor, another source/drain region of the sensing transistor is coupled to a reference node, and the current source is adapted to source a selected current to the bit line connection. 
     
     
         17 . The sense amplifier of  claim 14 , further comprising an isolation transistor coupled between the current source and the bit line connection. 
     
     
         18 . The sense amplifier of  claim 17 , wherein the isolation transistor comprises a control gate, wherein the isolation transistor further comprises a source/drain region coupled to the current source, and wherein the control gate of the isolation transistor is coupled to receive a voltage that is less than a voltage the current source can develop on the source/drain region of the isolation transistor. 
     
     
         19 . The sense amplifier of  claim 17 , wherein a control gate of the isolation transistor is coupled to an output of the sense amplifier. 
     
     
         20 . A memory device, comprising:
 a plurality of memory cells selectively coupled to a bit line; and   a sense amplifier selectively coupled to the bit line, the sense amplifier comprising:
 a current source coupled to a bit line connection; 
 a sensing transistor having a control gate coupled to the bit line connection; 
 a data latch coupled to a source/drain region of the sensing transistor; 
 wherein the current source comprises a transistor having a channel length greater than one and a half times the channel length of a conventional transistor of a semiconductor manufacturing process utilized to form the sense amplifier.