Invalid write prevention for stt-mram array

Abstract

In a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) a bit cell array can have a source line substantially parallel to a word line. The source line can be substantially perpendicular to bit lines. A source line control unit includes a common source line driver and a source line selector configured to select individual ones of the source lines. The source line driver and source line selector can be coupled in multiplexed relation. A bit line control unit includes a common bit line driver and a bit line selector in multiplexed relation. The bit line control unit includes a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and bit line select lines and bit lines.

What is claimed is: 
     
         1 . A method of making a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array comprising:
 forming a first source line of the bit cell array substantially parallel to a word line of the bit cell array, the first source line and the word line formed substantially perpendicular to bit lines of the bit cell array; and   forming a source line multiplexer adjacent to the bit cell array and coupled thereto, the source line multiplexer including a common source line driver and a source line selector configured to select individual ones of a plurality of source lines including the first source line.   
     
     
         2 . The method of making the STT-MRAM according to  claim 1 , further comprising:
 forming a bit line control unit adjacent to the bit cell array and coupled thereto and coupled to the source line control unit, the bit line control unit including a common bit line driver coupled to a plurality of the bit lines and a bit line selector coupled to the plurality of the bit lines, the common bit line driver and the bit line selector formed in multiplexed relation.   
     
     
         3 . The method of making the STT-MRAM according to  claim 2 , wherein the bit line control unit is formed from a positive channel metal oxide semiconductor (PMOS). 
     
     
         4 . The method of making the STT-MRAM according to  claim 2 , wherein the bit line control unit is formed with a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and each of a plurality of bit line select lines associated with the plurality of bit lines respectively, and each of the plurality of bit lines. 
     
     
         5 . The method of making the STT-MRAM according to  claim 1 , wherein the source line control unit is formed from a positive channel metal oxide semiconductor (PMOS). 
     
     
         6 . The method of making the STT-MRAM according to  claim 1 , wherein the source line control unit is formed with a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and each of a plurality of source line select lines associated with the plurality of source lines respectively, and each of the plurality of source lines. 
     
     
         7 . The method of making the STT-MRAM according to  claim 1 , further comprising:
 forming an invalid write prevention circuit between the bit line control unit and the source line control unit using a positive channel metal oxide semiconductor (PMOS) element.   
     
     
         8 . The method of making the STT-MRAM according to  claim 1 , further comprising integrating the STT-MRAM in at least one semiconductor die. 
     
     
         9 . The method of making the STT-MRAM according to  claim 1 , further comprising integrating the STT-RAM into an electronic device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data. unit, and a computer 
     
     
         10 . A method for writing data in a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) having a source line substantially parallel to a word line coupled to bit cells, the source line substantially perpendicular to bit lines coupled to the bit cells, the method comprising:
 establishing a low level on a bit line of a selected bit cell coupled to the word line of the first row of bit cells and the source line by turning on an negative channel metal oxide semiconductor (NMOS) element;   establishing a high level on bit lines of unselected ones of the bit cells coupled to the word line of the first bit cells and the source line by turning on positive channel metal oxide semiconductor (PMOS) elements; and   preventing an invalid write operation by the establishing the low level and the high level.   
     
     
         11 . The method of  claim 10 , wherein the high level is a supply voltage level and the low level is a ground level. 
     
     
         12 . The method of  claim 10 , wherein the establishing the low level on the bit line of the selected cell includes:
 generating a bit line select signal; and   activating a common bit line driver to establish the low level on the bit line of the selected cell based on the bit line select signal.   
     
     
         13 . The method of  claim 10 , wherein the bit line select signal is generated from a plurality of column address signals and a data high signal. 
     
     
         14 . The method of  claim 13 , wherein the common bit line driver is coupled to an associated bit line based on the bit line select signal. 
     
     
         15 . The method of  claim 13 , wherein the bit line select signal is derived from the column address signals. 
     
     
         16 . The method of  claim 13 , wherein the column select addresses signals and the complements of the column address signals are provided to a logic circuit with an output signal coupled to the common bit line driver. 
     
     
         17 . A Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) having a source line substantially parallel to a word line coupled to bit cells, the source line substantially perpendicular to the bit lines coupled to the bit cells, the STT-MRAM comprising:
 negative channel metal oxide semiconductor (NMOS) means for establishing a low voltage on a bit line of a selected bit cell coupled to the word line of the first row of bit cells and the source line;   positive channel metal oxide semiconductor (PMOS) means for establishing a high voltage on bit lines of unselected ones of the bit cells coupled to the word line of the bit cell and the source line; and   wherein the NMOS means and the PMOS means prevent an invalid write operation by establishing the low voltage and the high voltage.   
     
     
         18 . The STT-MRAM of  17 , wherein the NMOS means for establishing a low voltage on the bit line of the selected cell includes:
 means for generating bit line select signals; and   means for activating a common bit line driver to establish the low voltage on the bit line of the selected cell based on the bit line select signal.   
     
     
         19 . The STT-MRAM of  claim 18 , wherein the means for generating the bit line select signals receives a plurality of column address signals and a data high signal. 
     
     
         20 . The STT-MRAM of  claim 18 , wherein the bit line drivers are coupled to column address signals and complements of the column address signals. 
     
     
         21 . The STT-MRAM of  claim 17 , integrated in at least one semiconductor die. 
     
     
         22 . The STT-MRAM of  claim 17 , wherein the STT-MRAM is integrated into an electronic device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer. 
     
     
         23 . A method for writing data in a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) having a source line substantially parallel to a word line coupled to bit cells, the source line substantially perpendicular to bit lines coupled to the bit cells, the method comprising:
 a step for establishing a low level on a bit line of a selected bit cell coupled to the word line of the first row of bit cells and the source line by turning on an negative channel metal oxide semiconductor (NMOS) element;   a step for establishing a high level on bit lines of unselected ones of the bit cells coupled to the word line of the first bit cells and the source line by turning on positive channel metal oxide semiconductor (PMOS) elements; and   a step preventing an invalid write operation by the establishing the low level and the high level.   
     
     
         24 . The method of  claim 23 , wherein the high level is a supply voltage level and the low level is a ground level. 
     
     
         25 . The method of  claim 23 , wherein the step establishing the low level on the bit line of the selected cell includes:
 a step for generating a bit line select signal; and   a step for activating a common bit line driver to establish the low level on the bit line of the selected cell based on the bit line select signal.   
     
     
         26 . The method of  claim 25 , wherein the bit line select signal is generated from a plurality of column address signals and a data high signal. 
     
     
         27 . The method of  claim 26 , wherein the common bit line driver is coupled to an associated bit line based on the bit line select signal. 
     
     
         28 . The method of  claim 26 , wherein the bit line select signal is derived from the column address signals. 
     
     
         29 . The method of  claim 26 , wherein the column select addresses signals and the complements of the column address signals are provided to a logic circuit with an output signal coupled to the common bit line driver. 
     
     
         30 . A method of making a Spin Transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) bit cell array comprising:
 a step for forming a first source line of the bit cell array substantially parallel to a word line of the bit cell array, the first source line and the word line formed substantially perpendicular to bit lines of the bit cell array; and   a step for forming a source line multiplexer adjacent to the bit cell array and coupled thereto, the source line multiplexer including a common source line driver and a source line selector configured to select individual ones of a plurality of source lines including the first source line.   
     
     
         31 . The method of making the STT-MRAM according to  claim 30 , further comprising:
 a step for forming a bit line control unit adjacent to the bit cell array and coupled thereto and coupled to the source line control unit, the bit line control unit including a common bit line driver coupled to a plurality of the bit lines and a bit line selector coupled to the plurality of the bit lines, the common bit line driver and the bit line selector formed in multiplexed relation.   
     
     
         32 . The method of making the STT-MRAM according to  claim 31 , wherein the bit line control unit is formed from a positive channel metal oxide semiconductor (PMOS). 
     
     
         33 . The method of making the STT-MRAM according to  claim 31 , wherein the bit line control unit is formed with a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and each of a plurality of bit line select lines associated with the plurality of bit lines respectively, and each of the plurality of bit lines. 
     
     
         34 . The method of making the STT-MRAM according to  claim 30 , wherein the source line control unit is formed from a positive channel metal oxide semiconductor (PMOS). 
     
     
         35 . The method of making the STT-MRAM according to  claim 30 , wherein the source line control unit is formed with a positive channel metal oxide semiconductor (PMOS) element coupled between the common source line driver and each of a plurality of source line select lines associated with the plurality of source lines respectively, and each of the plurality of source lines. 
     
     
         36 . The method of making the STT-MRAM according to  claim 30 , further comprising:
 a step for forming an invalid write prevention circuit between the bit line control unit and the source line control unit using a positive channel metal oxide semiconductor (PMOS) element.   
     
     
         37 . The method of making the STT-MRAM according to  claim 30 , further comprising integrating the STT-MRAM in at least one semiconductor die.