Secure Memory Interface

Abstract

A secure memory interface includes a reader block, a writer block, and a mode selector for detecting fault injection into a memory device when a secure mode is activated. The mode selector activates or deactivates the secure mode using memory access information from a data processing unit. Thus, the data processing unit flexibly specifies the amount and location of the secure data stored into the memory device.

1 . A secure memory interface comprising:
 a writer block that generates a final write data to be written to a memory device from initial write data and error detection code when a secure mode is activated; and   a mode selector for activating or deactivating the secure mode using memory access information from a data processing unit.   
     
     
         2 . The secure memory interface of  claim 1 , wherein the writer block generates the final write data from the initial write data without the error detection code when the secure mode is deactivated. 
     
     
         3 . The secure memory interface of  claim 2 , wherein the memory access information includes an instruction name, and wherein the mode selector includes:
 an instruction decoder that activates the secure mode when the instruction name is for a secure write instruction, and that deactivates the secure mode when the instruction name is for a regular write instruction.   
     
     
         4 . The secure memory interface of  claim 2 , wherein the memory access information includes an address of the memory device to be accessed, and wherein the mode selector includes:
 an address decoder that activates the secure mode when the address of the memory device to be accessed is a secure address and that deactivates the secure mode when the address of the memory device to be accessed is a non-secure address.   
     
     
         5 . The secure memory interface of  claim 2 , wherein the memory access information includes a register name, and wherein the mode selector includes:
 a respective register flag that indicates whether the register name corresponds to activation or deactivation of the secure mode.   
     
     
         6 . The secure memory interface of  claim 2 , wherein the writer block includes:
 an encoder for generating the error detection code from at least one of a corresponding address and the initial write data; and   a mixer for generating mixed write data from the initial write data and the error detection code when the secure mode is activated and from the initial write data without the error detection code when the secure mode is deactivated;   wherein the mixed write data determines the final write data.   
     
     
         7 . The secure memory interface of  claim 6 , wherein the writer block further includes:
 a state machine for generating the final write data, a write enable signal, and a memory address of the memory device for storing the final write data, from the mixed data; and   a width selector for controlling the state machine to generate the final write data with a memory data width depending on at least one data width control signal that also controls operation of the encoder and the mixer,   and wherein the at least one data width control signal corresponds to a processing data width of the data processing unit.   
     
     
         8 . The secure memory interface of  claim 7 , wherein the data processing unit is a CPU separated from the memory device by a bus. 
     
     
         9 . The secure memory interface of  claim 8 , wherein the data processing unit and the memory device are fabricated as one integrated circuit chip. 
     
     
         10 . The secure memory interface of  claim 8 , wherein the data processing unit and the memory device are fabricated as two separate integrated circuit chips. 
     
     
         11 . A method of securely accessing a memory device, the method comprising:
 generating a final write data to be written to the memory device from initial write data and error detection code when a secure mode is activated; and   activating or deactivating the secure mode using memory access information from a data processing unit.   
     
     
         12 . The method of  claim 11 , further comprising:
 generating the final write data from the initial write data without the error detection code when the secure mode is deactivated.   
     
     
         13 . The method of  claim 12 , wherein the memory access information includes an instruction name, and wherein the method further includes:
 activating the secure mode when the instruction name is for a secure write instruction; and   deactivating the secure mode when the instruction name is for a regular write instruction.   
     
     
         14 . The method of  claim 12 , wherein the memory access information includes an address of the memory device to be accessed, and wherein the method further includes:
 activating the secure mode when the address of the memory device to be accessed is a secure address; and   deactivating the secure mode when the address of the memory device to be accessed is a non-secure address.   
     
     
         15 . The method of  claim 12 , wherein the memory access information includes a register name, and wherein a respective register flag indicates whether the register name corresponds to activation or deactivation of the secure mode. 
     
     
         16 . The method of  claim 12 , further comprising:
 generating the error detection code from at least one of the initial write data and a corresponding address; and   generating mixed write data from the initial write data and the error detection code when the secure mode is activated and from the initial write data without the error detection code when the secure mode is deactivated;   wherein the mixed write data determines the final write data.   
     
     
         17 . The method of  claim 16 , further comprising:
 generating the final write data, a write enable signal, and a memory address of the memory device for storing the final write data, from the mixed data; and   generating the final write data with a memory data width depending on at least one data width control signal,   wherein the at least one data width control signal corresponds to a processing data width of the data processing unit.   
     
     
         18 . The method of  claim 17 , wherein the data processing unit is a CPU separated from the memory device by a bus. 
     
     
         19 . The method of  claim 18 , wherein the data processing unit and the memory device are fabricated as one integrated circuit chip. 
     
     
         20 . The method of  claim 18 , wherein the data processing unit and the memory device are fabricated as two separate integrated circuit chips.