Variable unit delay circuit and clock generation circuit for semiconductor apparatus using the same

Abstract

A clock generation circuit includes, inter alia, a first phase detection block comparing initial phases of a reference clock signal and an output clock signal in response to an operation start signal, and outputting an initial phase difference detection signal corresponding to a comparison result; a second phase detection block comparing phases of the reference clock signal and the output clock signal, and outputting a phase detection signal corresponding to a comparison result; a variable unit delay block determined in a control range of the delay amount thereof in response to the initial phase difference detection signal, and delaying the reference clock signal by a delay amount corresponding to a voltage level of a control voltage and outputting the output clock signal; and a delay control block generating the control voltage which has the voltage level corresponding to the phase detection signal.

What is claimed is: 
     
         1 . A variable unit delay circuit comprising: a delayed pulse generation unit configured to generate a first delayed pulse signal which has a delayed transition timing after a rising edge of a reference clock signal in a high level duration of the reference clock signal and a second delayed pulse signal which has a delayed transition timing after a falling edge of the reference clock signal in a low level duration of the reference clock signal; a clock driving signal generation unit configured to generate a clock rising driving signal which is activated at the transition timing of the first delayed pulse signal and a clock falling driving signal which is activated at the transition timing of the second delayed pulse signal; and a clock output unit configured to output an output clock signal in response to the clock rising driving signal and the clock falling driving signal. 
     
     
         2 . The variable unit delay circuit according to  claim 1 , wherein delay amounts of the first and second delayed pulse signals are controlled based on a voltage level of a control voltage. 
     
     
         3 . The variable unit delay circuit according to  claim 1 , wherein the delayed pulse generation unit comprises: a first pull-up driving section configured to control a pull-up driving force to a first output terminal according to the voltage level of a control voltage; a first pull-down driving section configured to pull-down drive the first output terminal under the control of an inverted signal of the reference clock signal; a second pull-up driving section configured to control a pull-up driving force to a second output terminal according to the voltage level of the control voltage; and a second pull-down driving section configured to pull-down drive the second output terminal under the control of the reference clock signal. 
     
     
         4 . The variable unit delay circuit according to  claim 1 , wherein the clock driving signal generation unit comprises: a first logic section configured to logically combine the reference clock signal and the first delayed pulse signal and generate the clock rising driving signal; and a second logic section configured to logically combine the inverted signal of the reference clock signal and the second delayed pulse signal and generate the clock falling driving signal. 
     
     
         5 . The variable unit delay circuit according to  claim 1 , wherein the clock output unit comprises: a clock driving section configured to pull-up/pull-down drive a clock output terminal in response to the clock rising driving signal and the clock falling driving signal; and a latch section configured to latch a signal outputted from the clock output terminal. 
     
     
         6 . A variable unit delay circuit comprising: a clock dividing unit configured to divide a reference clock signal, and output a first divided clock signal and a second divided clock signal which is delayed more by one half cycle of the reference clock signal than the first divided clock signal; a first delayed pulse generation unit configured to generate a first delayed pulse signal which has a delayed transition timing after a rising edge of the first divided clock signal in a high level duration of the first divided clock signal and a second delayed pulse signal which has a delayed transition timing after a falling edge of the first divided clock signal in a low level duration of the first divided clock signal; a second delayed pulse generation unit configured to generate a third delayed pulse signal which has a delayed transition timing after a rising edge of the second divided clock signal in a high level duration of the second divided clock signal and a fourth delayed pulse signal which has a delayed transition timing after a falling edge of the second divided clock signal in a low level duration of the second divided clock signal; a clock rising driving signal generation unit configured to generate a clock rising driving signal which is activated at the respective transition timings of the first delayed pulse signal and the second delayed pulse signal; a clock falling driving signal generation unit configured to generate a clock falling driving signal which is activated at the respective transition timings of the third delayed pulse signal and the fourth delayed pulse signal; and a clock output unit configured to output an output clock signal in response to the clock rising driving signal and the clock falling driving signal. 
     
     
         7 . The variable unit delay circuit according to  claim 6 , wherein the first and second divided clock signals comprise signals which are generated by dividing by two the reference clock signal. 
     
     
         8 . The variable unit delay circuit according to  claim 6 , wherein delay amounts of the first through fourth delayed pulse signals are controlled based on a voltage level of a control voltage. 
     
     
         9 . The variable unit delay circuit according to  claim 6 , wherein the first delayed pulse generation unit comprises: a first pull-up driving section configured to control a pull-up driving force to a first output terminal according to the voltage level of the control voltage; a first pull-down driving section configured to pull-down drive the first output terminal under the control of an inverted signal of the first divided clock signal; a second pull-up driving section configured to control a pull-up driving force to a second output terminal according to the voltage level of the control voltage; and a second pull-down driving section configured to pull-down drive the second output terminal under the control of the first divided clock signal. 
     
     
         10 . The variable unit delay circuit according to  claim 9 , wherein the second delayed pulse generation unit comprises: a third pull-up driving section configured to control a pull-up driving force to a third output terminal according to the voltage level of the control voltage; a third pull-down driving section configured to pull-down drive the third output terminal under the control of an inverted signal of the second divided clock signal; a fourth pull-up driving section configured to control a pull-up driving force to a fourth output terminal according to the voltage level of the control voltage; and a fourth pull-down driving section configured to pull-down drive the fourth output terminal under the control of the second divided clock signal. 
     
     
         11 . The variable unit delay circuit according to  claim 6 , wherein the clock rising driving signal generation unit comprises: a first logic section configured to logically combine the first delayed pulse signal and the second delayed pulse signal and generate the clock rising driving signal. 
     
     
         12 . The variable unit delay circuit according to  claim 11 , wherein the clock falling driving signal generation unit comprises: a second logic section configured to logically combine the third delayed pulse signal and the fourth delayed pulse signal and generate the clock falling driving signal. 
     
     
         13 . The variable unit delay circuit according to  claim 6 , wherein the clock output unit comprises: a clock driving section configured to pull-up/pull-down drive a clock output terminal in response to the clock rising driving signal and the clock falling driving signal; and a latch section configured to latch a signal outputted from the clock output terminal. 
     
     
         14 . A variable unit delay circuit comprising: a delayed pulse generation unit configured to generate a first delayed pulse signal which has a delayed transition timing after a rising edge of a reference clock signal in a high level duration of the reference clock signal and a second delayed pulse signal which has a delayed transition timing after a falling edge of the reference clock signal in a low level duration of the reference clock signal; a clock rising driving signal generation unit configured to generate a clock rising driving signal which is activated at the transition timing of the first delayed pulse signal, when an initial phase difference detection signal is deactivated, and which is activated at the transition timing of the second delayed pulse signal, when the initial phase difference detection signal is activated; a clock falling driving signal generation unit configured to generate a clock falling driving signal which is activated at the transition timing of the second delayed pulse signal, when the initial phase difference detection signal is deactivated, and which is activated at the transition timing of the first delayed pulse signal, when the initial phase difference detection signal is activated; and a clock output unit configured to output an output clock signal in response to the clock rising driving signal and the clock falling driving signal. 
     
     
         15 . The variable unit delay circuit according to  claim 14 , wherein delay amounts of the first and second delayed pulse signals are controlled based on a voltage level of a control voltage. 
     
     
         16 . The variable unit delay circuit according to  claim 14 , wherein the initial phase difference detection signal comprises a signal which is activated in correspondence to a phase difference between the reference clock signal and the output clock signal. 
     
     
         17 . The variable unit delay circuit according to  claim 14 , wherein the delayed pulse generation unit comprises: a first pull-up driving section configured to control a pull-up driving force to a first output terminal according to the voltage level of a control voltage; a first pull-down driving section configured to pull-down drive the first output terminal under the control of an inverted signal of the reference clock signal; a second pull-up driving section configured to control a pull-up driving force to a second output terminal according to the voltage level of the control voltage; and a second pull-down driving section configured to pull-down drive the second output terminal under the control of the reference clock signal. 
     
     
         18 . The variable unit delay circuit according to  claim 14 , wherein the clock rising driving signal generation unit comprises: a first select section configured to output the clock rising driving signal which is activated in correspondence to the first delayed pulse signal or the second delayed pulse signal under the control of the initial phase difference detection signal. 
     
     
         19 . The variable unit delay circuit according to  claim 18 , wherein the clock falling driving signal generation unit comprises: a second select section configured to output the clock falling driving signal which is activated in correspondence to the first delayed pulse signal or the second delayed pulse signal under the control of the initial phase difference detection signal. 
     
     
         20 . The variable unit delay circuit according to  claim 14 , wherein the clock output unit comprises: a clock driving section configured to pull-up/pull-down drive a clock output terminal in response to the clock rising driving signal and the clock falling driving signal; and a latch section configured to latch a signal outputted from the clock output terminal.