Complex Semiconductor Packages and Methods of Fabricating the Same

Abstract

Disclosed are complex semiconductor packages, each including a large power module package which includes a small semiconductor package, and methods of manufacturing the complex semiconductor packages. An exemplary complex semiconductor package includes a first package including: a first packaging substrate; a plurality of first semiconductor chips disposed on the first packaging substrate; and a first sealing member covering the first semiconductor chips on the first packaging substrate; and at least one second package separated from the first packaging substrate, disposed in the first sealing member, and including second semiconductor chips.

1 .- 20 . (canceled) 
     
     
         21 . A complex semiconductor package, comprising:
 a first package having a first packaging substrate, one or more first semiconductor chips disposed on the first packaging substrate, and a first sealing member covering the one or more first semiconductor chips on the first packaging substrate;   a connecting member disposed in the first sealing member, the connecting member comprising a printed circuit board;   a second package comprising one or more second semiconductor chips, the second package being spaced apart from the first packaging substrate, the second package being disposed on the connecting member;   wherein the first packaging substrate comprises a direct bond copper substrate.   
     
     
         22 . The complex semiconductor package of  claim 21 , wherein the first packaging substrate includes:
 a ceramic insulating layer having a first surface and a second surface opposite the first surface;   a first conductive layer on the first surface of the ceramic insulating layer; and   a second conductive layer on the second surface of the ceramic insulating layer;   wherein the one or more first semiconductor chips are mounted on the first conductive layer.   
     
     
         23 . The complex semiconductor package of  claim 21 , wherein the first sealing member entirely covers the connecting member. 
     
     
         24 . The complex semiconductor package of  claim 21 , wherein the one or more second semiconductor chips are disposed in the first sealing member. 
     
     
         25 . The complex semiconductor package of  claim 21 , wherein the first package further comprises:
 a first lead that is partially exposed by the first sealing member and is electrically connected to the first packaging substrate; and   a second lead that is partially exposed by the first sealing member and is electrically connected to the connecting member.   
     
     
         26 . The complex semiconductor package of  claim 21 , wherein the first sealing member comprises an epoxy molding compound. 
     
     
         27 . The complex semiconductor package of  claim 21 , wherein the second package performs a different function from the first package and the second package has a different electrical capacity from the first package, and wherein the first and second packages are operated independently. 
     
     
         28 . The complex semiconductor package of  claim 27 , wherein the first package comprises a power module package comprising at least one power semiconductor chip, and the second package comprises a signal module package comprising a driver IC and a transistor IC. 
     
     
         29 . The complex semiconductor package of  claim 21 , wherein at least one of the one or more first semiconductor chips is electrically connected to the connecting member via a wire formed of Al or Au. 
     
     
         30 . A complex semiconductor package, comprising:
 a packaging substrate having a first surface and a second surface;   a first semiconductor chip disposed on the first surface of the packaging substrate;   a connecting member disposed apart from the packaging substrate;   a second semiconductor chip disposed on the connecting member;   a first lead connected to the packaging substrate;   a second lead connected to the connecting member; and   a sealing member on the first surface of the packaging substrate, the sealing member covering the connecting member, the second semiconductor chip, and the first and second leads;   wherein a portion of the first and second leads is exposed on an outer surface of the sealing member.   
     
     
         31 . The complex semiconductor package of  claim 30 , wherein the connecting member comprises a printed circuit board (PCB) and the packaging substrate comprises a direct bond copper substrate. 
     
     
         32 . The complex semiconductor package of  claim 30 , wherein the connecting member is electrically connected to the first semiconductor chip via a bonding wire.