US2013207252A1PendingUtilityA1

Semiconductor Device

54
Assignee: RENESAS ELECTRONICS CORPPriority: Apr 27, 2007Filed: Mar 18, 2013Published: Aug 15, 2013
Est. expiryApr 27, 2027(~0.7 yrs left)· nominal 20-yr term from priority
Inventors:Kuniharu MutoToshiyuki HataHiroshi SatoHiroi OkaOsamu Ikeda
H10W 90/766H10W 90/756H10W 90/736H10W 74/00H10W 72/07653H10W 72/07652H10W 72/07633H10W 72/07554H10W 72/07553H10W 72/07552H10W 72/07535H10W 72/07533H10W 72/07337H10W 72/07336H10W 72/5524H10W 72/5522H10W 72/5475H10W 72/5438H10W 72/5363H10W 72/952H10W 72/926H10W 72/923H10W 72/884H10W 72/871H10W 72/853H10W 72/652H10W 72/627H10W 72/537H10W 72/536H10W 72/534H10W 72/527H10W 72/353H10W 72/352H10W 72/325H10W 72/59H10W 46/607H10W 46/401H10W 46/103H10W 46/00H10W 72/0711H10W 72/016H10W 70/481H10W 70/466H10W 70/424H10W 70/411H10W 70/60H10W 70/457H10W 72/00H10D 64/256H10D 64/62H10D 62/105H10D 62/83H10D 30/668H10D 30/665H10D 12/481H10D 64/2527H01L 23/49582
54
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Claims

Abstract

To actualize a reduction in the on-resistance of a small surface mounted package having a power MOSFET sealed therein. A silicon chip is mounted on a die pad portion integrated with leads configuring a drain lead. The silicon chip has, on the main surface thereof, a source pad and a gate pad. The backside of the silicon chip configures a drain of a power MOSFET and bonded to the upper surface of a die pad portion via an Ag paste. A lead configuring a source lead is electrically coupled to the source pad via an Al ribbon, while a lead configuring a gate lead is electrically coupled to the gate pad via an Au wire.

Claims

exact text as granted — not AI-modified
1 - 19 . (canceled) 
     
     
         20 . A semiconductor chip comprising:
 a semiconductor chip having an obverse surface over which a first electrode pad is formed and a reverse surface opposite the obverse surface;   a die pad over which the semiconductor chip is mounted;   a first lead electrically connected to the semiconductor chip; and   an Al ribbon electrically connected to the first electrode pad of the semiconductor chip and the first lead;   a sealing body sealing the semiconductor chip, a part of the first lead, and the Al ribbon,   wherein the semiconductor chip is mounted over the die pad via an Ag paste such that the reverse surface of the semiconductor chip faces to the die pad, and   wherein a portion of the die pad which the Ag paste contacts is an Ag plated layer.   
     
     
         21 . The semiconductor device according to  claim 20 ,
 wherein a second electrode pad is formed over the obverse surface of the semiconductor chip,   wherein a second lead is electrically connected to the semiconductor chip,   wherein an Au wire is electrically connected to the second electrode pad of the semiconductor chip and the second lead, and   wherein a portion of the second lead to which the Au wire is electrically connected is the Ag plated layer.   
     
     
         22 . The semiconductor device according to  claim 20 ,
 wherein the first lead is formed by Cu, and   wherein a portion of the first lead to which the Al ribbon is electrically connected is not a plated layer.   
     
     
         23 . The semiconductor device according to  claim 20 ,
 wherein the semiconductor chip includes a trench gate power MOSFET, and   wherein the first electrode pad of the semiconductor chip is a source electrode pad.   
     
     
         24 . The semiconductor device according to  claim 20 ,
 wherein the semiconductor chip includes an insulated gate bipolar transistor, and   wherein the first electrode pad of the semiconductor chip is an emitter electrode pad.   
     
     
         25 . The semiconductor device according to  claim 21 ,
 wherein the semiconductor chip includes a trench gate power MOSFET, and   wherein the first electrode pad of the semiconductor chip is a source electrode pad and the second electrode pad of the semiconductor chip is a gate electrode pad.   
     
     
         26 . The semiconductor device according to  claim 25 ,
 wherein an area of the first electrode pad of the semiconductor chip is larger than an area of the second electrode pad of the semiconductor chip.   
     
     
         27 . The semiconductor device according to claim  21 ,
 wherein the semiconductor chip includes an insulated gate bipolar transistor, and   wherein the first electrode pad of the semiconductor chip is an emitter electrode pad and the second electrode pad of the semiconductor chip is a gate electrode pad.   
     
     
         28 . The semiconductor device according to  claim 27 ,
 wherein an area of the first electrode pad of the semiconductor chip is larger than an area of the second electrode pad of the semiconductor chip.   
     
     
         29 . A semiconductor chip comprising:
 a semiconductor chip having an obverse surface over which a first electrode pad is formed and a reverse surface opposite the obverse surface;   a die pad over which the semiconductor chip is mounted;   a first lead electrically connected to the semiconductor chip;   an Al ribbon electrically connected to the first electrode pad of the semiconductor chip and the first lead; and   a sealing body sealing the semiconductor chip, a part of the first lead, and the Al ribbon,   wherein the semiconductor chip is mounted over the die pad via an Ag paste such that the reverse surface of the semiconductor chip faces to the die pad, and   wherein a portion of the die pad which the Ag paste contacts is a Pd plated layer.   
     
     
         30 . The semiconductor device according to  claim 29 ,
 wherein a second electrode pad is formed over the obverse surface of the semiconductor chip,   wherein a second lead is electrically connected to the semiconductor chip,   wherein an Au wire is electrically connected to the second electrode pad of the semiconductor chip and the second lead, and   wherein a portion of the second lead to which the Au wire is electrically connected is the Pd plated layer.   
     
     
         31 . The semiconductor device according to  claim 29 ,
 wherein a portion of the first lead to which the Al ribbon is electrically connected is the Pd plated layer.   
     
     
         32 . The semiconductor device according to  claim 29 ,
 wherein the semiconductor chip includes a trench gate power MOSFET, and   wherein the first electrode pad of the semiconductor chip is a source electrode pad.   
     
     
         33 . The semiconductor device according to  claim 29 ,
 wherein the semiconductor chip includes an insulated gate bipolar transistor, and   wherein the first electrode pad of the semiconductor chip is an emitter electrode pad.   
     
     
         34 . The semiconductor device according to  claim 30 ,
 wherein the semiconductor chip includes a trench gate power MOSFET, and   wherein the first electrode pad of the semiconductor chip is a source electrode pad and the second electrode pad of the semiconductor chip is a gate electrode pad.   
     
     
         35 . The semiconductor device according to  claim 34 ,
 wherein an area of the first electrode pad of the semiconductor chip is larger than an area of the second electrode pad of the semiconductor chip.   
     
     
         36 . The semiconductor device according to  claim 30 ,
 wherein the semiconductor chip includes an insulated gate bipolar transistor, and   wherein the first electrode pad of the semiconductor chip is an emitter electrode pad and the second electrode pad of the semiconductor chip is a gate electrode pad.   
     
     
         37 . The semiconductor device according to  claim 36 ,
 wherein an area of the first electrode pad of the semiconductor chip is larger than an area of the second electrode pad of the semiconductor chip.

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