US2013200484A1PendingUtilityA1
Process for manufacturing a wafer by annealing of buried channels
Est. expiryJul 25, 2020(expired)· nominal 20-yr term from priority
H10P 95/906H10P 95/94H10W 10/021H10W 10/20H10W 10/181H10W 10/061H10W 10/17H10W 10/014H10P 90/1906H10D 62/115Y10S438/967H01L 29/0649H01L 21/76283
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Claims
Abstract
A process for manufacturing an SOI wafer, including the steps of: forming, in a wafer of semiconductor material, cavities delimiting structures of semiconductor material; thinning out the structures through a thermal process; and completely oxidizing the structures.
Claims
exact text as granted — not AI-modified1 .- 32 . (canceled)
33 . A semiconductor structure, comprising:
a closed cavity; and an epitaxial layer disposed over the cavity.
34 . The semiconductor structure of claim 33 wherein the closed cavity has a shape that includes a substantially circular cross-section.
35 . The semiconductor structure of claim 33 wherein the epitaxial layer surrounds the closed cavity.
36 . A semiconductor structure, comprising:
a region; a cavity disposed in the region and formed by
forming an opening in the region, and
annealing the region; and
an epitaxial layer disposed over the cavity.
37 . The semiconductor structure of claim 36 further comprising a circuit component disposed in the region and adjacent the cavity, the component operable to generate a signal.
38 . The semiconductor structure of claim 36 wherein forming the cavity includes growing an epitaxial layer to close the cavity before annealing the region.
39 . A system, comprising:
a first integrated circuit, comprising
a semiconductor structure, comprising:
a closed cavity; and
an epitaxial layer disposed over the cavity;
a second integrated circuit coupled to the first integrated circuit.
40 . The system of claim 39 wherein the first and second integrated circuits are disposed on a same die.
41 . The system of claim 39 wherein the first and second integrated circuits are disposed on respective dies.
42 . The system of claim 39 wherein the second integrated circuit comprises a controller.Join the waitlist — get patent alerts
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