Device, system and method of accessing data stored in a memory

Abstract

Device, system and method of accessing data stored in a memory. For example, a device may include a memory to store a plurality of data items to be accessed by a processor; a cache manager to manage, a cache within the memory, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of a respective data item and a pointer to an address of the data item; and a search module to receive from the cache manager an identifier of a requested data item, search the plurality of pointer entries for the identifier of the requested data item and, if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, provide the cache manager with the point from the detected entry. Other embodiments are described and claimed.

1 . A data processing system comprising:
 a first processor;   a first memory operably coupled to the first processor by a system bus;   a second processor;   a second memory operably coupled to the second processor;   a direct memory access (DMA) module operably coupled to the second processor and configured to transfer a plurality of data items from the first memory to the second memory;   a cache manager configured to manage a cache within the second memory, the cache including a plurality of pointer entries, each pointer entry including an identifier of one of the data items and a pointer to an address of said one data item; and   a search module configured to:
 search the plurality of pointer entries for the identifier of a requested data item, and 
 provide cache manager with the pointer from a pointer entry that includes an identifier of a respective data item that matches the identifier of the requested data item. 
   
     
     
         2 . The data processing system of  claim 1 , wherein the second memory stores a computer-readable program including instructions, wherein the instructions when executed by the second processor cause the second processor to perform functionality of the cache manager. 
     
     
         3 . The data processing system of  claim 1 , wherein the cache manager is implemented by a module called by the second processor. 
     
     
         4 . The data processing system of  claim 1 , wherein the search module comprises a hardware search module capable of searching the cache without using the second processor. 
     
     
         5 . The data processing system of  claim 1 , wherein the search module comprises a software search module executed in a third processor different from the second processor. 
     
     
         6 . The data processing system of  claim 1 , wherein the search module comprises one or more input registers, wherein the cache manager is configured to store the identifier of the requested data item in said one or more input registers. 
     
     
         7 . The data processing system of  claim 6 , wherein the search module further comprises:
 one or more output registers accessible by the cache manager; and   a searcher configured to store a predefined indicator in said one or more output registers if the identifier of the requested data item is not detected in the cache.   
     
     
         8 . The data processing system of  claim 7 , wherein the cache manager is further configured to, upon reading the predefined indicator in said one or more output registers, cause the DMA module to transfer the requested data item from the first memory to the second memory. 
     
     
         9 . A data processing method comprising:
 providing a first computer processor and a second computer processor;   providing a first memory operably coupled to the first processor;   transferring a plurality of data items from the first memory to the second memory using a direct memory access (DMA) module;   managing a cache within the second memory, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of one of the data items and a pointer to an address of said one data item;   searching the plurality of pointer entries for an identifier of a requested data item; and   if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, providing the pointer from the detected entry.   
     
     
         10 . The method of  claim 9 , further including storing in the second memory a computer-readable program including instructions, wherein said managing the cache includes executing the instructions by the second processor. 
     
     
         11 . The method of  claim 9 , wherein said searching includes executing search instructions in a third processor different from the second module. 
     
     
         12 . The method of  claim 9 , further comprising storing the identifier of the requested data item in one or more input registers. 
     
     
         13 . The method of  claim 12 , further comprising storing a predefined indicator in one or more output registers if the identifier of the requested data item is not detected in the cache. 
     
     
         14 . The method of  claim 13 , further comprising:
 reading the predefined indicator in said one or more output registers; and   responsive to said reading of the predefined indicator, causing the DMA module to transfer the requested data item from the first memory to the second memory.   
     
     
         15 . An apparatus comprising:
 a first computer readable medium including first instructions stored thereon, said first instructions when executed by a first computer processor causing the first computer processor to manage a cache within in a memory, the memory storing a plurality of data items, the cache including a plurality of pointer entries, wherein each pointer entry includes an identifier of a respective data item and a pointer to an address of the data item; and   a second computer readable medium including second instructions stored thereon, said second instructions when executed by a second computer processor causing a second computer processor to perform the operations of:
 searching the plurality of pointer entries for an identifier of a requested data item; and 
 if a pointer entry is detected to include an identifier of a respective data item that matches the identifier of the requested data item then, providing the pointer from the detected entry. 
   
     
     
         16 . The apparatus of  claim 15 , wherein:
 said first instructions when executed further cause the first computer processor to store the requested identifier and one or more search parameters in one or more input registers; and   said second instructions when executed further cause the second computer processor to:
 search the plurality of entries for the identifier of the requested data item based on the search parameters, and 
 perform said providing by storing the pointer from the detected entry in one or more output registers. 
   
     
     
         17 . The apparatus of  claim 16 , wherein said second instructions when executed further cause the second computer processor to store in the output registers an indication of an address of an empty entry in the cache. 
     
     
         18 . The apparatus of  claim 15 , wherein said first instructions when executed further cause the first computer processor to initialize the cache by storing an empty-address identifier in each entry of the cache. 
     
     
         19 . The apparatus of  claim 18 , wherein said first instructions when executed further cause the first computer processor to detect an address of an entry in the cache, which includes the empty-address identifier. 
     
     
         20 . The apparatus of  claim 19 , wherein said first instructions when executed further cause the first computer processor to add a pointer entry to the cache by replacing the empty-address identifier with the pointer entry.