Non-destructive self-reference spin-transfer torque memory

Abstract

A non-destructive self-reference spin-transfer torque memory unit is disclosed.

What is claimed is: 
     
         1 . A spin-transfer torque memory apparatus comprising:
 a magnetic tunnel junction data cell electrically between a bit line and a source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a polarized write current through the magnetic tunnel junction data cell;   an adjustable current driver electrically coupled to the bit line, the adjustable current driver configured to provide a provide a first read current and a second read current through the magnetic tunnel junction data cell, the first read current being less than the second read current;   a first voltage storage device electrically coupled to the bit line and configured to store a first bit line voltage formed by the first read current;   a second voltage storage device electrically coupled to the bit line and configured to store a second bit line voltage formed by the second read current; and   a differential sense amplifier electrically coupled to the first voltage storage device and electrically coupled to the second voltage storage device, the differential sense amplifier configured to compare the first bit line voltage with the second bit line voltage.   
     
     
         2 . A spin-transfer torque memory apparatus according to  claim 1 , wherein the first voltage storage device is a capacitor and the second voltage storage device is a capacitor. 
     
     
         3 . A spin-transfer torque memory apparatus according to  claim 2 , further comprising a third first voltage storage device electrically in series with the second voltage storage device. 
     
     
         4 . A spin-transfer torque memory apparatus according to  claim 3 , wherein the third voltage storage device is a capacitor. 
     
     
         5 . A spin-transfer torque memory apparatus according to  claim 2 , wherein the first voltage storage device and the second voltage storage device are NMOS or PMOS capacitors. 
     
     
         6 . A spin-transfer torque memory apparatus according to  claim 4 , wherein the third voltage storage device is a NMOS or PMOS capacitor. 
     
     
         7 . A spin-transfer torque memory apparatus according to  claim 4 , the second voltage storage device has a second capacitance value and the third voltage storage device has a third capacitance value and the second capacitance value is substantially the same as the third capacitance value. 
     
     
         8 . A spin-transfer torque memory apparatus according to  claim 3 , wherein the first voltage storage device and the second voltage storage device is a capacitor are in electrical parallel relation to each other. 
     
     
         9 . A spin-transfer torque memory apparatus according to  claim 3 , wherein the differential sense amplifier electrically coupled to an intermediate node electrically between the second voltage storage device and the third voltage storage device. 
     
     
         10 . A memory apparatus comprising:
 a magnetic tunnel junction data cell electrically between a bit line and a source line, the magnetic tunnel junction data cell is configured to switch between a high resistance state and a low resistance state by passing a write current through the magnetic tunnel junction data cell;   an adjustable current driver electrically coupled to the bit line, the adjustable current driver configured to provide a provide a first read current and a second read current through the magnetic tunnel junction data cell, the first read current being less than the second read current;   a first voltage storage device electrically coupled to the bit line and configured to store a first bit line voltage formed by the first read current;   a second voltage storage device electrically coupled to the bit line and configured to store a second bit line voltage formed by the second read current;   a third voltage storage device electrically coupled to the bit line and configured to store a second bit line voltage formed by the second read current, the second voltage storage device and the third voltage storage device are electrically connected in series; and   a differential sense amplifier electrically coupled to the first voltage storage device and electrically coupled to the second voltage storage device, the differential sense amplifier configured to compare the first bit line voltage with the second bit line voltage.   
     
     
         11 . A memory apparatus according to  claim 10 , wherein the first voltage storage device is a capacitor and the second voltage storage device is a capacitor. 
     
     
         12 . A memory apparatus according to  claim 10 , wherein the third voltage storage device is a capacitor. 
     
     
         13 . A memory apparatus according to  claim 11 , wherein the first voltage storage device and the second voltage storage device are NMOS or PMOS capacitors. 
     
     
         14 . A memory apparatus according to  claim 12 , wherein the third voltage storage device is a NMOS or PMOS capacitor. 
     
     
         15 . A memory apparatus according to  claim 12 , the second voltage storage device has a second capacitance value and the third voltage storage device has a third capacitance value and the second capacitance value is substantially the same as the third capacitance value. 
     
     
         16 . A memory apparatus according to  claim 10 , wherein the first voltage storage device and the second voltage storage device is a capacitor are in electrical parallel relation to each other. 
     
     
         17 . A memory apparatus according to  claim 10 , wherein the differential sense amplifier electrically coupled to an intermediate node electrically between the second voltage storage device and the third voltage storage device.