Integrated circuit and method of forming an integrated circuit

Abstract

An integrated circuit includes a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.

What is claimed is: 
     
         1 . An integrated circuit, comprising:
 a first trench disposed in a semiconductor material, wherein a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.   
     
     
         2 . The integrated circuit according to  claim 1 , wherein
 the first trench further comprises an extension region extending in a depth direction of the semiconductor material.   
     
     
         3 . The integrated circuit according to  claim 2 , wherein a width of the extension region measured in a plane parallel to the surface of the semiconductor material is smaller than the width of the first trench in the lower portion of the first trench. 
     
     
         4 . The integrated circuit according to  claim 1 , wherein
 the first trench is filled with an insulating material.   
     
     
         5 . The integrated circuit according to  claim 1 , wherein
 the first trench is filled with an insulating material disposed adjacent to the semiconductor material, the integrated circuit further comprising a conductive filling insulated from the semiconductor material by the insulating material.   
     
     
         6 . The integrated circuit according to  claim 5 , further comprising a second trench which extends to a depth smaller than a depth of the first trench. 
     
     
         7 . The integrated circuit according to  claim 1 , wherein
 the first trench extends to a depth of more than 25 μm.   
     
     
         8 . The integrated circuit according to  claim 1 , further comprising circuit elements insulated from each other by the first trench. 
     
     
         9 . The integrated circuit according to  claim 1 , wherein
 the semiconductor material is a monocrystalline semiconductor substrate.   
     
     
         10 . The integrated circuit according to  claim 1 , wherein
 the semiconductor material is polycrystalline or amorphous semiconductor material disposed over a semiconductor substrate.   
     
     
         11 . The integrated circuit according to  claim 5 , wherein
 the first trench is a deep isolation trench in smart power technology.   
     
     
         12 . The integrated circuit according to  claim 5 , wherein
 the first trench is a contact hole.   
     
     
         13 . A method of forming an integrated circuit, comprising:
 forming a first trench in a semiconductor material so that a width of the first trench in an upper portion of the first trench adjacent to a surface of the semiconductor material is smaller than a width of the first trench in a lower portion of the first trench, the lower portion being disposed within the semiconductor material, each width being measured in a plane parallel to a surface of the semiconductor material, each width denoting a distance between inner faces of remaining semiconductor material portions or between outer faces of a filling disposed in the first trench, or between an inner face of a remaining semiconductor material portion and an outer face of a filling disposed in the first trench.   
     
     
         14 . The method of  claim 13 ,
 wherein forming the first trench comprises:   a first etching process, wherein an etching rate in a depth direction of the semiconductor material is larger than an etching rate in a plane parallel to the surface of the semiconductor material; and   a second etching process, wherein an etching rate in the depth direction is approximately equal to the etching rate in the direction parallel to the surface of the semiconductor material.   
     
     
         15 . The method of  claim 14 , further comprising:
 performing a third etching process after the second etching process, wherein an etching rate in the depth direction is larger than an etching rate in a plane parallel to the surface of the semiconductor material.   
     
     
         16 . The method according to  claim 14 , wherein the etching processes are performed in a single etching device. 
     
     
         17 . The method according to  claim 14 , further comprising filling an insulating material in the first trench. 
     
     
         18 . The method according to  claim 14 , further comprising:
 forming an insulating layer on a sidewall of the first trench; and   forming a conductive filling in the first trench.   
     
     
         19 . The method according to  claim 13 , wherein the semiconductor material is a monocrystalline semiconductor substrate. 
     
     
         20 . The method according to  claim 13 , wherein the semiconductor material is polycrystalline or amorphous semiconductor material disposed over a semiconductor substrate. 
     
     
         21 . An integrated circuit, comprising:
 a first trench disposed in a semiconductor material, the first trench comprising a curved first sidewall, wherein an angle δ between a tangent to the first sidewall in an upper portion of the first trench and a surface of the remaining semiconductor material is smaller than 90°, the upper portion of the first trench being adjacent to the surface of the semiconductor material, and an angle γ between a tangent to the first sidewall in a lower portion of the first trench and the surface of the remaining semiconductor material is greater than the angle δ, the lower portion being disposed within the semiconductor material.   
     
     
         22 . The integrated circuit according to  claim 21 , wherein
 the first trench further comprises an extension region extending in a depth direction of the semiconductor material, the extension region having a second sidewall, and wherein an angle between the second sidewall and the surface of the semiconductor material is greater than the angle δ.   
     
     
         23 . The integrated circuit according to  claim 21 , wherein
 the first trench is filled with an insulating material.   
     
     
         24 . The integrated circuit according to  claim 21 , wherein
 the first trench is filled with an insulating material disposed adjacent to the semiconductor material, the integrated circuit further comprising a conductive filling insulated from the semiconductor material by the insulating material.