Architectures for an Implantable Stimulator Device Having a Plurality of Electrode Driver Integrated Circuits with Shorted Electrode Outputs

Abstract

Disclosed is a new architecture for an IPG having a master and slave electrode driver integrated circuits. The electrode outputs on the integrated circuits are wired together. Each integrated circuit can be programmed to provide pulses with different frequencies. Active timing channels in each of the master and slave integrated circuits are programmed to provide the desired pulses, while shadow timing channels in the master and slave are programmed with the timing data from the active timing channels in the other integrated circuit so that each chip knows when the other is providing a pulse, so that each chip can disable its recovery circuitry so as not to defeat those pulses. In the event of pulse overlap at a given electrode, the currents provided by each chip will add at the affected electrode. Compliance voltage generation is dictated by an algorithm to find an optimal compliance voltage even during periods when pulses are overlapping.

What is claimed is: 
     
         1 . An implantable stimulator device, comprising:
 a plurality of integrated circuits each comprising a plurality of electrode outputs, each integrated circuit further comprising stimulation circuitry configured to provide a current at the electrode outputs,   wherein corresponding electrode outputs on each of the plurality of integrated circuits are shorted together.   
     
     
         2 . The device of  claim 1 , wherein the plurality of integrated circuits are housed in a single package, and wherein the corresponding electrode outputs are shorted within the package. 
     
     
         3 . The device of  claim 2 , wherein the plurality of integrated circuits are vertically stacked in the single package. 
     
     
         4 . The device of  claim 1 , wherein a first of the plurality of integrated circuits comprises a master integrated circuit, and a second of the plurality of integrated circuits comprises a slave integrated circuit to the master integrated circuit. 
     
     
         5 . The device of  claim 4 , wherein the master and slave integrated circuits are bond programmable. 
     
     
         6 . The device of  claim 4 , further comprising a microcontroller, and wherein the microcontroller, the master integrated circuit, and the slave integrated circuit communicate by a bus in accordance with a bus protocol. 
     
     
         7 . The device of  claim 1 , wherein the stimulation circuitry of each of the plurality of integrated circuits is programmed with timing information concerning when it is configured to provide current at the electrode outputs. 
     
     
         8 . The device of  claim 7 , wherein the stimulation circuitry of each of the plurality of integrated circuits is further programmed with the timing information from all of the other integrated circuits. 
     
     
         9 . The device of  claim 8 , wherein the timing information comprises current pulse frequency and pulse width. 
     
     
         10 . The device of  claim 1 , wherein the stimulation circuitry is configured to provide the current at the electrode outputs at different frequencies in each of the plurality of integrated circuits. 
     
     
         11 . The device of  claim 1 , wherein the electrode outputs are coupled to electrodes for delivering the current provided by each stimulation circuitry to the tissue of a patient. 
     
     
         12 . The device of  claim 11 , wherein the electrode outputs are coupled to the electrodes via decoupling capacitors. 
     
     
         13 . The device of  claim 1 , wherein the plurality of integrated circuits are identical. 
     
     
         14 . An implantable stimulator device, comprising:
 a plurality of electrode nodes;   first stimulation circuitry programmed to provide first current pulses of a first frequency, and to select a first plurality of the plurality of electrode nodes to receive the first current pulses; and   second stimulation circuitry programmed to provide second current pulses of a second frequency, and to select a second plurality of the plurality of electrode nodes to receive the second current pulses,   wherein if an electrode node is common to both the selected first plurality of electrode nodes and the second plurality of electrode nodes, the first and second current pulses are added at the common electrode node when they overlap.   
     
     
         15 . The device of  claim 14 , wherein the first stimulation circuitry comprises a first integrated circuit, and wherein the second stimulation circuitry comprises a second integrated circuit. 
     
     
         16 . The device of  claim 15 , wherein the first and second integrated circuits are housed in a single package. 
     
     
         17 . The device of  claim 14 , wherein the first stimulation circuitry is programmed with timing information of the second current pulses, and wherein the second stimulation circuitry is programmed with timing information of the first current pulses. 
     
     
         18 . The device of  claim 14 , wherein the first stimulation circuitry further comprises first recovery circuitry for recovering charge after provision of the first current pulses, and wherein the second stimulation circuitry further comprises second recovery circuitry for recovering charge after provision of the second current pulses. 
     
     
         19 . The device of  claim 18 , wherein the first recovery circuitry is configured to be inactivated during the second current pulses, and wherein the second recovery circuitry is configured to be inactivated during the first current pulses. 
     
     
         20 . The device of  claim 14 , wherein the electrode nodes are coupled to electrodes for delivering the current provided by each stimulation circuitry to the tissue of a patient. 
     
     
         21 . The device of  claim 20 , wherein the electrode outputs are coupled to the electrodes via decoupling capacitors. 
     
     
         22 . The device of  claim 14 , further comprising:
 a case for housing the electrode nodes and the first and second stimulation circuitries; and   at least one array comprising electrodes for stimulating a patient's tissue,   wherein one electrode node is coupled to the case, and wherein the other of the plurality of electrode nodes are coupled to electrodes on the at least one electrode array.   
     
     
         23 . An implantable stimulator device, comprising:
 a conductive case;   a first electrode array;   a second electrode array;   a first integrated circuit within the conductive case, wherein the first integrated circuit is configured to provide first current pulses at a first frequency to cause a first current to flow between the first electrode array and the case; and   a second integrated circuit within the conductive case, wherein the second integrated circuit is configured to provide second current pulses at a second frequency to cause a second current to flow between the second electrode array and the case,   wherein the first and second current pulses can overlap in time.   
     
     
         24 . The device of  claim 23 , wherein the first and second currents are added at the conductive case when the first and second pulse overlap in time. 
     
     
         25 . The device of  claim 23 , wherein the first and second integrated circuits are housed in a single package. 
     
     
         26 . The device of  claim 25 , wherein the first and second integrated circuits are vertically stacked in the single package. 
     
     
         27 . The device of  claim 23 , further comprising a microcontroller, and wherein the microcontroller, the first integrated circuit, and the second integrated circuit communicate by a bus in accordance with a bus protocol. 
     
     
         28 . The device of  claim 23 , wherein the first integrated circuit is programmed with first timing information concerning when it is configured to provide the first current pulses, and wherein the second integrated circuit is programmed with second timing information concerning when it is configured to provide the second current pulses. 
     
     
         29 . The device of  claim 28 , wherein the first integrated circuit is further programmed with the second timing information, and wherein the second integrated circuit is further programmed with the first timing information. 
     
     
         30 . The device of  claim 29 , wherein the first and second timing information comprises current pulse frequency and pulse width. 
     
     
         31 . The device of  claim 23 , wherein the plurality of integrated circuits are identical.