Method and apparatus to serialize parallel data input values

Abstract

A method includes applying a clock signal having an uneven duty cycle to a control input of at least one selection element of a selection circuit having a tree structure that includes multiple selection elements. The tree structure includes a data input tier and a data output tier.

What is claimed is:  
     
         1 . A method comprising:
 receiving a first data input at a combinatorial logic circuit;   receiving a second data input at the combinatorial logic circuit;   receiving a first signal at a first control input of the combinatorial logic circuit, the first signal formed by combining a first clock signal having a first phase with a second clock signal having a second phase;   receiving a second signal at a second control input of the combinatorial logic circuit, the second signal formed by combining a third clock signal having a third phase with a fourth clock signal having a fourth phase; and   selecting one of the first data input and the second data input as a selected output based on the first signal and the second signal.   
     
     
         2 . The method of  claim 1 , wherein the combinatorial logic circuit includes at least one NAND multiplexer. 
     
     
         3 . The method of  claim 1 , wherein a first duty cycle corresponding to the first signal is less than a fifty percent duty cycle, wherein a second duty cycle corresponding to the second signal is greater than the fifty percent duty cycle. 
     
     
         4 . The method of  claim 3 , wherein the first duty cycle and the second duty cycle are complementary. 
     
     
         5 . The method of  claim 1 , wherein the first, second, third, and fourth clock signals each have a fifty percent duty cycle. 
     
     
         6 . The method of  claim 1 , wherein combining the first clock signal with the second clock signal further comprises performing an AND operation on the first and second clock signals, wherein combining the third clock signal with the fourth clock signal further comprises performing an OR operation on the third and fourth clock signals. 
     
     
         7 . The method of  claim 1 , further comprising:
 receiving the first and second data inputs from a parallel interface, wherein the selected output provides serial data.   
     
     
         8 . The method of  claim 1 , wherein receiving the first and second data inputs, receiving the first and second signals, and selecting one of the first and second data inputs are performed at a serializer integrated in a semiconductor die. 
     
     
         9 . A method comprising:
 applying a clock signal having an uneven duty cycle to a control input of at least one selection element of a selection circuit having a tree structure that includes multiple selection elements, wherein the tree structure includes a data input tier and a data output tier.   
     
     
         10 . The method of  claim 9 , wherein the tree structure is a balanced tree structure that includes a root selection element having a first input from a first selection element of a first branch of the tree structure and a second input from a second selection element of a second branch of the tree structure, wherein the first branch and the second branch have an equal number of selection elements. 
     
     
         11 . The method of  claim 9 , wherein the tree structure includes an intermediate tier. 
     
     
         12 . The method of  claim 9 , wherein the data input tier and the data output tier each include at least one of the multiple selection elements. 
     
     
         13 . The method of  claim 9 , wherein data inputs from a parallel interface are received at the data input tier, and wherein serial data is output by the data output tier. 
     
     
         14 . The method of  claim 13 , wherein the parallel interface provides seven data inputs, and wherein the duty cycle is about a forty-two percent duty cycle. 
     
     
         15 . The method of  claim 9 , wherein each of the selection elements is a latch-free circuit. 
     
     
         16 . The method of  claim 15 , wherein the latch-free circuit includes a plurality of combinatorial logic elements. 
     
     
         17 . The method of  claim 16 , wherein the combinatorial logic elements include NAND logic elements. 
     
     
         18 . The method of  claim 9 , wherein the uneven duty cycle corresponds to a number of data inputs. 
     
     
         19 . The method of  claim 9 , wherein the selection circuit is a serializer integrated in a semiconductor die. 
     
     
         20 . An apparatus comprising:
 an input set of selection elements in an input tier of a tree structure; and   a selection element in an output tier of the tree structure,   wherein the input tier includes inputs to receive input data from a parallel interface, wherein the output tier includes an output to provide serial output data, and wherein at least one of the selection elements includes a latch-free circuit that includes NAND logic circuits.   
     
     
         21 . The apparatus of  claim 20 , further comprising:
 an intermediate set of selection elements in an intermediate tier of the tree structure, wherein the intermediate tier is operative to select between data received from the input tier and to provide selected data to the output tier.   
     
     
         22 . The apparatus of  claim 20  integrated in at least one semiconductor die. 
     
     
         23 . The apparatus of  claim 20 , further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the tree structure is integrated. 
     
     
         24 . An apparatus comprising:
 an input set of selection elements in an input tier of a tree structure; and   a selection element in an output tier of the tree structure,   wherein the output tier includes a delay element, and wherein the delay element and the selection element include a similar combinatorial logic structure.   
     
     
         25 . The apparatus of  claim 24 , further comprising:
 an intermediate set of selection elements in an intermediate tier of e tree structure.   
     
     
         26 . The apparatus of  claim 24  integrated in at least one semiconductor die. 
     
     
         27 . The apparatus of  claim 24 , further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), fixed location data unit, and a computer, into which the tree structure is integrated. 
     
     
         28 . An apparatus comprising:
 means for selecting first data in a first tier of a tree structure; and   means for selecting second data in a second tier of the tree structure,   wherein the first tier includes inputs to receive the first data from a parallel interface, wherein the second tier includes an output to provide serial output data, and wherein at least one of the means for selecting first data and means for selecting second data includes a latch-free circuit that includes NAND logic circuits.   
     
     
         29 . The apparatus of  claim 28  integrated in at least one semiconductor die. 
     
     
         30 . The apparatus of  claim 28 , further comprising a device selected from the group consisting of a set top box, a music player, a video player, an entertainment unit, a navigation device, a communications device, a personal digital assistant (PDA), a fixed location data unit, and a computer, into which the tree structure is integrated. 
     
     
         31 . A method comprising:
 a first step for receiving a first data input at a combinatorial logic circuit;   a second step for receiving a second data input at the combinatorial logic circuit;   a third step for receiving a first signal at a first control input of the combinatorial logic circuit, the first signal formed by combining a first clock signal having a first phase with a second clock signal having a second phase;   a fourth step for receiving a second signal at a second control input of the combinatorial logic circuit, the second signal formed by combining a third clock signal having a third phase with a fourth clock signal having a fourth phase; and   a fifth step for selecting one of the first data input and the second data input as a selected output based on the first multi-phase clock signal and the second multi-phase clock signal.   
     
     
         32 . The method of  claim 31 , wherein combining the first clock signal with the second clock signal further comprises performing an AND operation on the first and second clock signals, wherein combining the third clock signal with the fourth clock signal further comprises performing an OR operation on the third and fourth clock signals. 
     
     
         33 . The method of  claim 31 , wherein the first, second, third, fourth, and fifth steps are performed by a serializer integrated into an electronic device. 
     
     
         34 . A method comprising:
 receiving a data file comprising design information corresponding to a semiconductor device; and   fabricating the semiconductor device according to the design information, wherein the semiconductor device comprises:
 an input set of selection elements in an input tier of a tree structure; and 
 a selection element in an output tier of the tree structure, 
 wherein the input tier comprises inputs to receive input data from a parallel interface, wherein the output tier comprises an output to provide serial output data, and wherein at least one of the selection elements comprises a latch-free circuit that comprises NAND logic circuits. 
   
     
     
         35 . The method of  claim 34 , wherein the data file has a GDSII format. 
     
     
         36 . The method of  claim 34 , wherein the data file has a GERBER format.