Semiconductor device and method of fabricating the same

Abstract

In a method of fabricating a semiconductor device on a substrate having thereon a conductive layer, the conductive layer is patterned to form a plurality of opened regions. A gate insulation layer is formed on a side wall of each of the opened regions. A pillar pattern is formed in each opened region. On each pillar pattern, a gate electrode, which encloses the pillar pattern, is formed by removing the conductive layer between the pillar patterns.

1 - 15 . (canceled) 
     
     
         16 . A semiconductor device, comprising:
 a substrate having at least one pillar pattern grown thereon,   a gate insulation layer extending around and covering a side wall of the at least one pillar pattern,   a gate electrode extending around and partially covering the gate insulation layer, and   a side wall protection layer positioned above the gate electrode, extending around and partially covering the gate insulation layer.   
     
     
         17 . The device of  claim 16 , wherein the side wall of the at least one pillar pattern is substantially normal to a plane of the substrate throughout an entire height of said at least one pillar pattern. 
     
     
         18 . The device of  claim 16 , further comprising
 at least one insulation layer extending around and partially covering the gate insulation layer,   wherein said gate electrode, said side wall protection layer and said at least one insulation layer completely cover said gate insulation layer over an entire height of the at least one pillar pattern.   
     
     
         19 . The device of  claim 18 , wherein said at least one insulation layer comprises a first insulation layer between the gate electrode and the substrate, and a second insulation layer between the gate electrode and the side wall protection layer. 
     
     
         20 . The device of  claim 16 , further comprising
 a gate hard mask layer formed above and completely covering upper surfaces of the side wall protection layer, the gate insulation layer, and the at least one pillar pattern.