Discrete power transistor package having solderless dbc to leadframe attach

Abstract

A packaged power transistor device includes a Direct-Bonded Copper (“DBC”) substrate. Contact pads of a first lead are attached with solderless welds to a metal layer of the DBC substrate. In a first example, the solderless welds are ultrasonic welds. In a second example, the solderless welds are laser welds. A single power transistor realized on a single semiconductor die is attached to the DBC substrate. In one example, a first bond pad of the die is wire bonded to a second lead, and a second bond pad of the die is wire bonded to a third lead. The die, the wire bonds, and the metal layer of the DBC substrate are covered with an amount of plastic encapsulant. Lead trimming is performed to separate the first, second and third leads from the remainder of a leadframe, the result being the packaged power transistor device.

What is claimed is: 
     
         1 . A method comprising:
 attaching a first metal layer of a direct-bonded copper (“DBC”) substrate to at least one lead with a solderless weld and thereby forming an assembly, wherein the DBC substrate comprises an insulative layer disposed between the first metal layer and a second metal layer;   attaching one and only one power semiconductor integrated circuit die to the first metal layer of the assembly; and   incorporating the assembly into a packaged power integrated circuit device such that the packaged power integrated circuit device comprises only one semiconductor die.   
     
     
         2 . The method of  claim 1 , wherein the packaged power integrated circuit device conforms to a TO-247 package outline. 
     
     
         3 . The method of  claim 1 , wherein the attaching involves ultrasonically welding the DBC substrate to the at least one lead. 
     
     
         4 . The method of  claim 3 , wherein the welding is carried out by clamping the DBC substrate and the at least one lead together with not more than about 0.05 Mpa, and wherein the welding is carried out using ultrasonic vibrations of an amplitude of less than approximately 20 micrometers. 
     
     
         5 . The method of  claim 1 , wherein the attaching involves laser welding the DBC substrate to the at least one lead. 
     
     
         6 . The method of  claim 1 , wherein the first metal layer has a thickness of at least 0.25 millimeters. 
     
     
         7 . A packaged power integrated circuit device comprising:
 a direct-bonded copper (“DBC”) substrate comprising an insulative layer disposed between the first metal layer and a second metal layer;   one and only one power semiconductor integrated circuit die attached to the first metal layer;   at least one lead that is mechanically and electrically coupled to the first metal layer with a solderless weld; and   an amount of encapsulant surrounding the one and only one power semiconductor integrated circuit die and at least the first metal layer, and leaving at least a portion of the second metal layer of the DBC substrate exposed to form a back side of the packaged power integrated circuit device, and leaving a portion of the lead exposed, wherein the second metal layer is electrically insulated from the first metal layer.   
     
     
         8 . The packaged power integrated circuit device of  claim 7 , wherein the solderless weld is an ultrasonic weld. 
     
     
         9 . The packaged power integrated circuit device of  claim 8 , wherein the first metal layer has a thickness of at least 0.25 millimeters. 
     
     
         10 . The packaged power integrated circuit device of  claim 7 , wherein the solderless weld is a laser weld. 
     
     
         11 . The packaged power integrated circuit device of  claim 7 , wherein the packaged power integrated circuit device conforms to a TO-247 package outline. 
     
     
         12 . The packaged power integrated circuit device of  claim 7 , wherein the one and only one power semiconductor integrated circuit die is taken from the group consisting of: a power rectifier die, a power regulator die, a silicon controlled rectifier die, a power bipolar transistor integrated circuit die, a power insulated gate bipolar transistor circuit die, a power field effect transistor integrated circuit die. 
     
     
         13 . The packaged power integrated circuit device of  claim 7 , wherein the packaged power integrated circuit device includes three leads, and wherein the back side of the packaged power integrated circuit device is electrically insulated from each of the three leads. 
     
     
         14 . The packaged power integrated circuit device of  claim 7 , wherein there is no solder disposed between the first metal layer of the DBC substrate and the one and only one power semiconductor integrated circuit die. 
     
     
         15 . A packaged power integrated circuit device comprising:
 a direct-bonded copper (“DBC”) substrate comprising a ceramic layer and a metal layer disposed on the ceramic layer;   one and only one power semiconductor integrated circuit die attached to the first metal layer;   an amount of encapsulant covering the one and only one power semiconductor integrated circuit die and at least the first metal layer;   a first lead that is mechanically connected to the first metal layer with a solderless weld;   a second lead that is wire bonded to the one and only one power semiconductor integrated circuit die; and   a third lead that is wire bonded to the one and only one power semiconductor integrated circuit die, wherein the first, second, and third leads extend parallel to one another from the amount of encapsulant.   
     
     
         16 . The packaged power integrated circuit device of  claim 15 , wherein the first lead has a first contact pad portion and a second contact pad portion, wherein the first contact pad portion has an upper surface that extends in a plane that is substantially parallel to a plane of an upper surface of the metal layer of the DBC substrate, wherein the upper surface of the first contact portion has a pattern of indentations, wherein the second contact pad portion has an upper surface that extends in the plane that is substantially parallel to the plane of the upper surface of the metal layer of the DBC substrate, wherein the upper surface of the second contact portion has a pattern of indentations. 
     
     
         17 . The packaged power integrated circuit device of  claim 15 , wherein the first lead has a first contact pad portion and a second contact pad portion, wherein the first contact pad portion has an upper surface that extends in a plane that is substantially parallel to a plane of an upper surface of the metal layer of the DBC substrate, wherein the upper surface of the first contact portion has a pattern of mound-shaped protrusions, wherein the second contact pad portion has an upper surface that extends in the plane that is substantially parallel to the plane of the upper surface of the metal layer of the DBC substrate, wherein the upper surface of the second contact portion has a pattern of mound-shaped protrusions. 
     
     
         18 . The packaged power integrated circuit device of  claim 17 , wherein the pattern of mound-shaped protrusions on the first contact portion is a row, and wherein the pattern of mound-shaped protrusions on the second contact portion is a row.