Semiconductor device

Abstract

A method for fabricating a semiconductor device includes: forming a fin-type semiconductor region on a substrate; and introducing an n-type impurity into at least a side of the fin-type semiconductor region by a plasma doping process, thereby forming an n-type impurity region in the side of the fin-type semiconductor region. In the introducing the n-type impurity, when a source power in the plasma doping process is denoted by a character Y [W], the supply of a gas containing the n-type impurity per unit time and per unit volume is set greater than or equal to 5.1×10 −8 /((1.7 2.51 /2 4.51 )×(Y/500)) [mol/(min·L·sec)], and the supply of a diluent gas per unit time and per unit volume is set greater than or equal to 1.7×10 −4 /(20 2.51 /2 4.51 )×(Y/500)) [mol/(min·L·sec)].

1 - 18 . (canceled) 
     
     
         19 . A semiconductor device comprising:
 a fin-type semiconductor region formed on a substrate; and   an n-type impurity region formed in a side of the fin-type semiconductor region,   wherein a spreading resistance of the n-type impurity region is less than 9.0×10 4 Ω.   
     
     
         20 . The semiconductor device of  claim 19 , wherein the spreading resistance of the n-type impurity region is less than or equal to 6.3×10 4 Ω. 
     
     
         21 . The semiconductor device of  claim 20 , wherein the spreading resistance of the n-type impurity region is less than or equal to 3.6×10 4 Ω. 
     
     
         22 . The semiconductor device of  claim 19 , wherein the n-type impurity region contains As. 
     
     
         23 . The semiconductor device of  claim 19 , wherein
 the n-type impurity region is an extension region, and   a gate electrode is formed to cover a part of the fin-type semiconductor region adjacent to the n-type impurity region.   
     
     
         24 . The semiconductor device of  claim 19 , wherein
 the n-type impurity region is a source/drain region,   a gate electrode is formed to cover a part of the fin-type semiconductor region apart from the n-type impurity region, and   an insulative sidewall spacer is formed to cover a side of the gate electrode and a portion of the fin-type semiconductor region located between the n-type impurity region and the gate electrode.   
     
     
         25 . The semiconductor device of  claim 19 , wherein a width of the fin-type semiconductor region along a gate width is less than or equal to 15 nm.