Structure and method for reducing vertical crack propagation

Abstract

A semiconductor device and a method of fabricating the same, includes vertically stacked layers on an insulator. Each of the layers includes a first dielectric insulator portion, a first metal conductor embedded within the first dielectric insulator portion, a first nitride cap covering the first metal conductor, a second dielectric insulator portion, a second metal conductor embedded within the second dielectric insulator portion, and a second nitride cap covering the second metal conductor. The first and second metal conductors form first vertically stacked conductor layers and second vertically stacked conductor layers. The first vertically stacked conductor layers are proximate the second vertically stacked conductor layers, and at least one air gap is positioned between the first vertically stacked conductor layers and the second vertically stacked conductor layers. An upper semiconductor layer covers the first vertically stacked conductor layers, the air gap and the second plurality of vertically stacked conductor layers.

What is claimed is: 
     
         1 . A method of fabricating a semiconductor device, said method comprising:
 forming an insulator;   forming a plurality of vertically stacked insulator layers on said insulator in a process that includes embedding first metal conductors and second metal conductors in each of said stacked insulator layers to form a plurality of first vertically stacked metal layers and a plurality of second vertically stacked metal layers proximate said first vertically stacked layers; and   forming at least one air gap in an inter-stack material of said vertically stacked insulator layers between said first vertically stacked metal layers and said second vertically stacked metal layers.   
     
     
         2 . The method according to  claim 1 , further comprising:
 positioning said air gap less than 10 μm between a first side edge of said first plurality of vertically stacked metal layers and a second side edge said second plurality of vertically stacked metal layers.   
     
     
         3 . The method according to  claim 1 , further comprising:
 forming a second air gap in said inter-stack material,   a portion of said inter-stack material between said first air gap and said second air gap comprising a dielectric insulation material.   
     
     
         4 . The method according to  claim 1 , further comprising:
 forming at least one metal fill in said inter-stack material,   a portion of said inter-stack material being positioned between said metal fill and said air gap comprising dielectric insulation material.   
     
     
         5 . The method according to  claim 1 , said forming each of said first plurality of vertically stacked metal layers further comprising:
 forming a first dielectric insulator portion;   embedding one of said first metal conductors within said first dielectric insulator portion; and   covering said first metal conductor with a first nitride cap;   said forming of each of said second plurality of vertically stacked metal layers further comprising:   forming a second dielectric insulator portion;   embedding one of said second metal conductors within said second dielectric insulator portion; and   covering said second metal conductor with a second nitride cap.   
     
     
         6 . A method of fabricating a semiconductor device, said method comprising:
 forming an insulator;   forming a plurality of layers on said insulator, each of said layers including a dielectric insulator portion, a first metal conductor and a second metal conductor proximate said first metal conductor, and a nitride cap;   forming a first vertically stacked metal structure by vertically aligning each of said first metal conductors of each of said layers with each other as said layers are successively formed on said insulator, and forming a second vertically stacked metal structure by vertically aligning each of said second metal conductors as said layers are successively formed on said insulator; and   etching at least one air gap within said layers between said first vertically stacked metal structure and said second vertically stacked metal structure.   
     
     
         7 . The method according to  claim 6 , further comprising:
 positioning said air gap less than 10 μm between a first side edge of said first vertically stacked metal structure and a second side edge said second vertically stacked metal structure.   
     
     
         8 . The method according to  claim 6 , further comprising:
 etching a second air gap within said layers between said first vertically stacked metal structure and said second vertically stacked metal structure,   a portion of said layers between said first air gap and said second air gap comprising dielectric insulation material.   
     
     
         9 . The method according to  claim 6 , further comprising:
 depositing at least one metal fill positioned between said first vertically stacked metal structure and said second vertically stacked metal structure,   a portion of said layers between said metal fill and said air gap comprising dielectric insulation material.   
     
     
         10 . The method according to  claim 6 , further comprising forming a plurality of alternating air gaps and metal fill structures within said layers between said first vertically stacked metal structure and said second vertically stacked metal structure. 
     
     
         11 . A method of fabricating a semiconductor device, said method comprising:
 forming an insulator;   forming a plurality of vertically stacked insulator layers on said insulator in a process that includes embedding first metal conductors and second metal conductors in each of said stacked insulator layers to form a plurality of first vertically stacked metal layers and a plurality of second vertically stacked metal layers proximate said first vertically stacked layers; and   forming at least one air gap in an inter-stack material of said vertically stacked insulator layers between a first side edge of said first vertically stacked metal layers and a second side edge of said second vertically stacked metal layers.   
     
     
         12 . The method according to  claim 11 , further comprising:
 positioning said air gap less than 10 μm between said first plurality of vertically stacked metal layers and said second plurality of vertically stacked metal layers.   
     
     
         13 . The method according to  claim 11 , further comprising:
 forming a second air gap in said inter-stack material,   a portion of said inter-stack material between said first air gap and said second air gap comprising a dielectric insulation material.   
     
     
         14 . The method according to  claim 11 , further comprising:
 forming at least one metal fill in said inter-stack material,   a portion of said inter-stack material being positioned between said metal fill and said air gap comprising dielectric insulation material.   
     
     
         15 . The method according to  claim 11 , said forming each of said first plurality of vertically stacked metal layers further comprising:
 forming a first dielectric insulator portion;   embedding one of said first metal conductors within said first dielectric insulator portion; and   covering said first metal conductor with a first nitride cap;   said forming of each of said second plurality of vertically stacked metal layers further comprising:   forming a second dielectric insulator portion;   embedding one of said second metal conductors within said second dielectric insulator portion; and   covering said second metal conductor with a second nitride cap.