Soi structures having a sacrificial oxide layer

Abstract

Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.

1 . A silicon on insulator structure comprising a handle wafer, a silicon device layer, a dielectric layer between the handle wafer and the silicon device layer, and a sacrificial oxide layer, the silicon device layer being bonded to the dielectric layer at a first surface and being bonded to the sacrificial oxide layer at a second surface which forms a sacrificial oxide-silicon device layer interface, the device layer comprising metal atoms of a first type, wherein at least about 50% of the metal atoms of the first type are positioned in the device layer at the interface. 
     
     
         2 . The silicon on insulator structure as set forth in  claim 1  wherein the metal atoms of a first type are selected from the group consisting of nickel atoms, copper atoms and cobalt atoms. 
     
     
         3 . The silicon on insulator structure as set forth in  claim 1  wherein the metal atoms of a first type are nickel atoms. 
     
     
         4 . The silicon on insulator structure as set forth in  claim 3  wherein at least about 70% of the metal atoms of the first type are positioned in the device layer at the interface. 
     
     
         5 . The silicon on insulator structure as set forth in  claim 3  wherein at least about 55% of the metal atoms of the first type are positioned in the device layer at the interface. 
     
     
         6 . The silicon on insulator structure as set forth in  claim 3  wherein at least about 60% of the metal atoms of the first type are positioned in the device layer at the interface. 
     
     
         7 . The silicon on insulator structure as set forth in  claim 1  wherein the silicon device layer is less than about 200 nm thick. 
     
     
         8 . The silicon on insulator structure as set forth in  claim 1  wherein the silicon device layer is less than about 75 nm thick. 
     
     
         9 . The silicon on insulator structure as set forth in  claim 1  wherein the dielectric layer is composed of SiO 2 .