Soi structures with reduced metal content

Abstract

Methods for producing silicon on insulator structures with a reduced metal content in the device layer thereof are disclosed. Silicon on insulator structures with a reduced metal content are also disclosed.

What is claimed is: 
     
         1 . A silicon on insulator structure comprising a handle wafer, a silicon device layer having a front surface, and a dielectric layer between the handle wafer and the silicon device layer, the dielectric layer and silicon device layer forming an interface between the dielectric layer and silicon device layer, the silicon on insulator structure having the amount of metal in the device layer reduced by:
 forming a sacrificial oxide layer on the front surface of the silicon device layer, the sacrificial oxide layer and the silicon device layer forming an interface between the sacrificial oxide layer and the silicon device layer;   heating the silicon on insulator structure having a sacrificial oxide layer thereon to a temperature T 1  sufficient to dissolve all metal precipitates present in the device layer for a time t 1  sufficient to allow metal atoms to evenly disperse throughout the device layer, wherein the temperature T 1  is less than a temperature at which the metal atoms cross the sacrificial oxide layer-silicon device layer interface and enter the sacrificial oxide layer;   cooling the silicon on insulator structure from T 1  to a temperature T 2  at which the metal atoms are substantially immobile in silicon at an average cooling rate R to cause metal atoms to dissolve to the sacrificial oxide layer-silicon device layer interface and the silicon device layer-dielectric layer interface, the cooling rate being sufficiently high enough to cause substantially no metal precipitation to occur in the silicon device layer during cooling; and   removing the sacrificial oxide layer and a portion of the metal atoms at the sacrificial oxide layer-silicon device layer interface from the front surface of the silicon device layer;   wherein the silicon device layer comprises metal of a first type in an amount at or below the solubility limit of the metal in silicon at temperature T 1  after the amount of metal in the device layer has been reduced.   
     
     
         2 . The silicon on insulator structure as set forth in  claim 1  wherein the metal content in the silicon device layer is reduced by heating the silicon on insulator structure for a time sufficient to allow the average lateral diffusion distance of the metal atoms to exceed the thickness of the device layer. 
     
     
         3 . The silicon on insulator structure as set forth in  claim 2  wherein the metal content in the silicon device layer is reduced by heating the silicon on insulator structure for a time sufficient to allow the lateral diffusion distance of the metal atoms to exceed the thickness of the device layer by at least about 100 times. 
     
     
         4 . The silicon on insulator structure as set forth in  claim 2  wherein the metal content in the silicon device layer is reduced by heating the silicon on insulator structure for a time sufficient to allow the lateral diffusion distance of the metal atoms to exceed the thickness of the device layer by at least about 1000 times. 
     
     
         5 . The silicon on insulator structure as set forth in  claim 1  wherein the temperature at the sacrificial oxide layer-silicon device layer interface exceeds the temperature at the silicon device layer-dielectric layer interface during cooling such that more metal atoms are positioned at the sacrificial oxide layer-silicon device layer interface than the silicon device layer-dielectric layer interface. 
     
     
         6 . The silicon on insulator structure as set forth in  claim 1  wherein the metal is selected from the group consisting of nickel, copper and cobalt. 
     
     
         7 . The silicon on insulator structure as set forth in  claim 1  wherein the metal is nickel. 
     
     
         8 . The silicon on insulator structure as set forth in  claim 7  wherein T 1  is at least about 490° C. 
     
     
         9 . The silicon on insulator structure as set forth in  claim 1  wherein T 1  is at least the temperature at which the metal dissolves in the device layer and is no more than about 25° C. greater than the temperature at which the metal completely dissolves in the device layer. 
     
     
         10 . The silicon on insulator structure as set forth in  claim 7  wherein the time t 1  at which the silicon on insulator structure is heated is at least about 1 minute. 
     
     
         11 . The silicon on insulator structure as set forth in  claim 7  wherein the cooling rate R is at least about 0.3° C./min. 
     
     
         12 . The silicon on insulator structure as set forth in  claim 7  wherein T 2  is about 440° C. 
     
     
         13 . The silicon on insulator structure as set forth in  claim 7  wherein T 2  is about 440° C. or less. 
     
     
         14 . The silicon on insulator structure as set forth in  claim 1  wherein the sacrificial oxide layer is formed by exposing the structure to ambient air to form a native oxide layer. 
     
     
         15 . The silicon on insulator structure as set forth in  claim 1  wherein the sacrificial oxide layer is formed by heating the wafer in an oxygen-containing atmosphere. 
     
     
         16 . The silicon on insulator structure as set forth in  claim 1  wherein the silicon device layer is less than about 200 nm thick. 
     
     
         17 . The silicon on insulator structure as set forth in  claim 1  wherein the silicon device layer is less than about 75 nm thick. 
     
     
         18 . The silicon on insulator structure as set forth in  claim 1  wherein the initial concentration of nickel in the silicon on insulator structure is at least about 1×10 10  atoms/cm 3 . 
     
     
         19 . The silicon on insulator structure as set forth in  claim 1  wherein the concentration of nickel in the silicon device layer is at least about 1×10 10  atoms/cm 3 . 
     
     
         20 . The silicon on insulator structure as set forth in  claim 1  wherein the sacrificial oxide layer forming step, heating step, cooling step and sacrificial oxide layer removal step are repeated for about 2 cycles or more to further reduce the amount of metal in the silicon device layer. 
     
     
         21 . The silicon on insulator structure as set forth in  claim 1  wherein the dielectric layer is composed of SiO 2 . 
     
     
         22 . The silicon on insulator structure as set forth in  claim 1  wherein the sacrificial oxide layer and a portion of the metal atoms at the sacrificial oxide layer-silicon device layer interface are removed by contacting the silicon on insulator structure with the sacrificial layer thereon is contacted with an etching solution.