Methods and Systems for Repairing Interior Device Layers in Three-Dimensional Integrated Circuits

Abstract

A three-dimensional integrated circuit (3D-IC) includes a stack of semiconductor wafers, each of which includes a substrate and a device layer. Programmable components, such as memory arrays or logic circuits, are formed within the device layers. Some of the programmable components are redundant, and can be substituted for defective components by programming passive memory elements in a separate conductive layer provided for this purpose. The separate conductive layer is devoid of active devices, and is therefore relatively reliable and inexpensive.

What is claimed is: 
     
         1 . A three-dimensional integrated circuit (3D-IC) comprising:
 a first semiconductor substrate having a first device layer, the first device layer including first programmable components and a first control port coupled to the first programmable components, the first control port to selectively enable the first programmable components;   a second semiconductor substrate disposed on and bonded to the first semiconductor substrate, the second semiconductor substrate having a second device layer that includes second programmable components and a second control port coupled to the second programmable components, the second control port to selectively enable the second programmable components, the second semiconductor substrate including conductive vias extending from the first control port through the second semiconductor substrate; and   a conductive layer devoid of active devices and including first passive memory elements coupled to the first control port by the conductive vias and second passive memory elements coupled to the second control port.   
     
     
         2 . The 3D-IC of  claim 1 , wherein the conductive layer is disposed on a third substrate bonded to the second semiconductor substrate. 
     
     
         3 . The 3D-IC of  claim 2 , wherein the second substrate is of a semiconductor. 
     
     
         4 . The 3D-IC of  claim 2 , wherein the conductive layer is in contact with the third substrate. 
     
     
         5 . The 3D-IC of  claim 1 , wherein the first and second semiconductor substrates include configuration circuitry, and wherein the first and second control ports extend to the configuration circuitry. 
     
     
         6 . The 3D-IC of  claim 1 , wherein the first device layer includes a power-supply node and the second semiconductor substrate includes a supply via extending through the second semiconductor substrate to the conductive layer. 
     
     
         7 . The 3D-IC of  claim 1 , wherein the first programmable components include an individually powered memory bank having a supply node connected to the conductive layer by a corresponding one of the vias. 
     
     
         8 . The 3D-IC of  claim 1 , wherein the programmable components include spare memory arrays, and wherein fuse latches assign addresses to the memory arrays based on program states of the passive elements. 
     
     
         9 . The 3D-IC of  claim 1 , the first substrate including memory test ports and the second substrate including second vias extending from the test ports to the conductive layer. 
     
     
         10 . The 3D-IC of  claim 1 , wherein the passive memory elements are electrically programmable. 
     
     
         11 . The 3D-IC of  claim 10 , wherein the passive memory elements include at least one of fuses or antifuses. 
     
     
         12 . The 3D-IC of  claim 1 , further comprising configuration circuitry, wherein the first and second control ports are coupled to the respective first and second programmable components via the configuration circuitry. 
     
     
         13 . The 3D-IC of  claim 1 , wherein the first and second programmable components include a memory array. 
     
     
         14 . The 3D-IC of  claim 1 , wherein the passive memory element comprise alternative present or absent conductors. 
     
     
         15 . A method of fabricating an integrated circuit, the method comprising:
 bonding a semiconductor substrates, each substrate having a device layer including programmable components and a control port coupled to the programmable components to selectively enable the programmable components;   bonding a conductive layer to the semiconductor substrates, the conductive layer devoid of active devices and including passive memory elements coupled to the control ports by conductive vias that extend through at least one of the substrates;   testing the programmable components to identify defective ones of the programmable components; and   programming the passive memory elements to disregard the defective ones of the programmable components.   
     
     
         16 . The method of  claim 15 , wherein the bonding of the semiconductor substrates and the conductive layer occur simultaneously. 
     
     
         17 . The method of  claim 15 , wherein the programmable components include arrays of memory cells. 
     
     
         18 . The method of  claim 15 , wherein the passive memory elements include at least one of fuses and antifuses. 
     
     
         19 . The method of  claim 15 , wherein the conductive layer overlays a second substrate. 
     
     
         20 . The method of  claim 19 , wherein the second substrate is a semiconductor substrate. 
     
     
         21 . The method of  claim 15 , wherein programming the passive memory elements includes customizing a metal layer using at least one of metallization options, laser fuses, customizable masks, and e-beam customization of the metal layer. 
     
     
         22 . An integrated circuit (IC) comprising:
 stacked semiconductor substrates, each substrate supporting programmable components and including conductive vias; and   a conductive layer overlaying the stacked semiconductor substrates and devoid of active devices, the conductive layer including passive memory elements coupled to the programmable components by the conductive vias.   
     
     
         23 . The IC of  claim 22 , wherein the passive memory elements store state information, and wherein the state information selectively disables a subset of the programmable components. 
     
     
         24 . The IC of  claim 22 , wherein the conductive layer is disposed on a layer of insulator or semiconductor bonded to the stacked substrates.