Vector simd processor

Abstract

Operation parallelism of a data processor is enhanced by floating-point inner product execution units compatible with single instruction multiple data (SIMD). An operating system that can significantly enhance the level of operation parallelism per instruction while maintaining efficiency of floating-point length-4 vector inner product execution units is implemented. The floating-point length-4 vector inner product execution units are defined in the minimum width (32 bits for single precision) even where an extensive operating system becomes available, and compose the inner product execution units to be compatible with SIMD. The mutually augmenting effects of the inner product execution units and SIMD-compatible composition enhances the level of operation parallelism dramatically. Composition of the floating-point length-4 vector inner product execution units to calculate the sum of the inner product of length-4 vectors and scalar to be compatible with SIMD of four in parallel results in a processing capability of 32 FLOPS per cycle.

1 . A data processor having an SIMD type execution unit:
 said data processor having an instruction to cause said SIMD type execution unit to process vector data.   
     
     
         2 . A data processor, as claimed in  claim 1 , wherein:
 said SIMD type execution unit has a plurality of execution units for performing multiply-add operations on floating-point numbers.   
     
     
         3 . A data processor for executing instructions in an instruction set and having an SIMD type execution unit, wherein:
 said instruction set includes an instruction for causing said SIMD type execution unit to operate on vector data.   
     
     
         4 . A data processor, as claimed in  claim 3 , wherein:
 said SIMD type execution unit has a plurality of execution units for performing multiply-add operations on floating-point numbers.   
     
     
         5 - 12 . (canceled)