Reduction of thickness variations of a threshold semiconductor alloy by reducing patterning non-uniformities prior to depositing the semiconductor alloy

Abstract

The growth rate in a selective epitaxial growth process for depositing a threshold adjusting semiconductor alloy, such as a silicon/germanium alloy, may be enhanced by performing a plasma-assisted etch process prior to performing the selective epitaxial growth process. For example, a mask layer may be patterned on the basis of the plasma-assisted etch process, thereby simultaneously providing superior device topography during the subsequent growth process. Hence, the threshold adjusting material may be deposited with enhanced thickness uniformity, thereby reducing overall threshold variability.

1 - 20 . (canceled) 
     
     
         21 . A semiconductor device, comprising:
 an active silicon-containing semiconductor region;   an isolation structure laterally enclosing said active silicon-containing semiconductor region, said isolation structure having a first edge and a second edge, said first and second edges defining a width of said active silicon-containing semiconductor region;   a threshold adjusting semiconductor alloy formed on said active silicon-containing semiconductor region, said threshold adjusting semiconductor alloy extending from said first edge to said second edge and having a thickness with a variation of approximately 5 percent or less; and   a gate electrode structure comprising a high-k gate insulation layer and a metal-containing electrode material formed on said high-k gate insulation layer.   
     
     
         22 . The semiconductor device of  claim 21 , wherein an average thickness of said threshold adjusting semiconductor alloy is approximately 10 nm or less. 
     
     
         23 . The semiconductor device of  claim 22 , wherein said threshold adjusting semiconductor alloy comprises a silicon/germanium alloy with a germanium concentration of approximately 20 atomic percent or more. 
     
     
         24 . The semiconductor device of  claim 21 , wherein the threshold adjusting semiconductor alloy has a thickness with a variation of approximately 3% or less. 
     
     
         25 . The semiconductor device of  claim 24 , wherein the threshold adjusting semiconductor alloy has a thickness with a variation of approximately 2% or less. 
     
     
         26 . A semiconductor device, comprising:
 an active silicon-containing semiconductor region;   an isolation structure laterally enclosing said active silicon-containing semiconductor region, said isolation structure having a first edge and a second edge, said first and second edges defining a width of said active silicon-containing semiconductor region;   a threshold adjusting semiconductor alloy formed on said active silicon-containing semiconductor region, said threshold adjusting semiconductor alloy extending from said first edge to said second edge and having a thickness with a variation of approximately 5 percent or less; and   a plurality of transistors formed over the threshold adjusting semiconductor alloy in the active silicon-containing semiconductor region.   
     
     
         27 . The semiconductor device of  claim 26 , wherein an average thickness of said threshold adjusting semiconductor alloy is approximately 10 nm or less. 
     
     
         28 . The semiconductor device of  claim 27 , wherein said threshold adjusting semiconductor alloy comprises a silicon/germanium alloy with a germanium concentration of approximately 20 atomic percent or more. 
     
     
         29 . The semiconductor device of  claim 26 , wherein the threshold adjusting semiconductor alloy has a thickness with a variation of approximately 3% or less. 
     
     
         30 . The semiconductor device of  claim 29 , wherein the threshold adjusting semiconductor alloy has a thickness with a variation of approximately 2% or less. 
     
     
         31 . The semiconductor device of  claim 26 , wherein each of the plurality of transistors comprises a gate electrode structure comprising a high-k gate insulation layer and a metal-containing electrode material formed on said high-k gate insulation layer. 
     
     
         32 . The semiconductor device of  claim 26 , wherein the plurality of transistors comprise a plurality of P-channel transistors.