US2013159598A1PendingUtilityA1

Method of massive parallel pattern matching against a progressively-exhaustive knowledge base of patterns

Individually held — no corporate assignee on recordPriority: Feb 24, 2009Filed: Nov 7, 2012Published: Jun 20, 2013
Est. expiryFeb 24, 2029(~2.6 yrs left)· nominal 20-yr term from priority
G06F 12/0246G06V 30/1904G06V 30/1463G06V 30/2268G06V 30/194G06V 30/10G06V 10/95
41
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A method of pattern and image recognition and identification includes building a data store of known patterns or images having known attributes and comparing those patterns to unknown patterns. The data store and comparison processing may be distributed across processors. A digital pattern recognition engine on each of the processors has the ability to compare a known pattern from the data store and an unknown pattern and compare the two patterns to determine whether the patterns constitute a match based on match criteria. If the comparison indicates a match, the match may be communicated to the data store and added as a known pattern with detected attributes to the data store. If the comparison does not indicate a match, the pattern may be flagged, transmitted to manual recognition, or further processed using character thresholding or cutting or slicing the pattern.

Claims

exact text as granted — not AI-modified
1 . A nano processor comprising:
 non-volatile memory being the nano processor's own dedicated solid state disk serving as permanent storage for the nano processor, in which the non-volatile memory performs the same functions as a dedicated hard drive performs for a typical stand alone computer;   random access memory functioning as if it were a computer's own dedicated random access memory;   one or more levels of cache memory serving as onboard processor cache memory for very fast data access and data processing, as is customary for processors to have very fast onboard static cache memory.   
     
     
         2 . A multi processor apparatus comprising a plurality of nano processors according to  claim 1 , each of said nano processors arranged such that each of the nano processors are able to operate and do processing independent of one another and communicate with one another in a distributed or non-distributed parallel fashion.

Join the waitlist — get patent alerts

Track US2013159598A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.