US2013159578A1PendingUtilityA1

System and method for Automatic Hardware Interrupt Handling

Assignee: MIPS TECH INCPriority: Jul 30, 2010Filed: Feb 4, 2013Published: Jun 20, 2013
Est. expiryJul 30, 2030(~4 yrs left)· nominal 20-yr term from priority
G06F 9/30101G06F 13/26G06F 9/327G06F 9/4812G06F 9/30116
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Claims

Abstract

A processing system is provided consisting of an interrupt pin, multiple registers, a stack pointer, and an automatic interrupt system. The multiple registers store a number of processor states values. When the system detects an interrupt on the interrupt pin the system prepares to enter an exception mode where the automatic interrupt system causes an interrupt vector to be fetched, the stack pointer to be updated, and the processor state values to be read in parallel from the registers and stored in memory locations based on the updated stack pointer, prior to the execution of an interrupt service routine. A method for automatic hardware interrupt handling is also presented.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A method of interrupt handling, comprising:
 determining a privilege level associated with a first interrupt;   updating a first stack pointer register with a value copied from a first fixed register,   storing a value associated with the first interrupt in a first memory address at a location identified by the first stack pointer register, and   disallowing access to the first fixed register from a process operating at a second privilege level, wherein the second privilege level is lower than the privilege level of the first interrupt.   
     
     
         2 . The method of  claim 1 , further comprising:
 determining a privilege level of a second interrupt;   updating a second stack pointer register with a value copied from a third stack pointer register associated with an interrupted process operating at a third privilege level, wherein the third privilege level is equal to the privilege level of the second interrupt;   modifying the value in the second stack pointer register, and   storing a value associated with the second interrupt in a second memory address at a location identified by the second stack pointer register.

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