Multi-processor architecture and method

Abstract

Embodiments of a multi-processor architecture and method are described herein. Embodiments provide alternatives to the use of an external bridge integrated circuit (IC) architecture. For example, an embodiment multiplexes a peripheral bus such that multiple processors can use one peripheral interface slot without requiring an external bridge IC. Embodiments are usable with known bus protocols.

What is claimed is: 
     
         1 . A system comprising:
 a peripheral component connector coupled to a peripheral component bus; and   a plurality of peripheral components coupled directly to the peripheral component connector via a plurality of respective transmit/receive (TX/RX) lanes such that the plurality of peripheral components connect and communicate with the peripheral component bus as one peripheral device coupled to the peripheral component connector;   wherein the plurality of peripheral components comprise a plurality of processors; and   wherein the plurality of peripheral components are further coupled directly to each other via respective transmit/receive (TX/RX) lanes and each processor, receiving data from the peripheral component connector, forwards all of the data received from the peripheral component connector to the remaining processors.   
     
     
         2 . The system of  claim 1 , wherein the peripheral component determines whether to receive the data using an address. 
     
     
         3 . The system of  claim 1 , wherein the plurality of processors comprises at least one of the processors is a graphics processing unit (GPU). 
     
     
         4 . The system of  claim 1 , wherein the peripheral component connector is a peripheral component interconnect express slot. 
     
     
         5 . The system of  claim 2 , wherein the each peripheral component is configured to receive all of the data transmitted via the peripheral component connector and to decide which data is applicable. 
     
     
         6 . The system of  claim 1 , wherein the peripheral bus comprises a peripheral component interconnect express bus to which the processors are directly coupled. 
     
     
         7 . A computer-readable medium having instructions stored thereon, that when executed in a multi-processor system cause a method to be performed, the method comprising:
 communicating bus data between a plurality of processors and a peripheral bus via respective groups of transmit/receive (TX/RX) lanes of the bus;   communicating data between the plurality of processors via TX/RX lanes that are not coupled to the bus;   determining one of the plurality of processors to communicate with the peripheral bus using an address; and   wherein for each processor receiving data from the peripheral bus, forwarding all of the data received from the peripheral bus to the processors.   
     
     
         8 . The method of  claim 7  determining one of the plurality of processors to communicate with the peripheral bus using an address. 
     
     
         9 . The method of  claim 7 , wherein the plurality of processors comprise at least one GPU, and wherein the peripheral bus comprises a peripheral component interconnect express bus to which the processors are directly coupled wherein the step of communicating data between the plurality of processors is communicating bus data. 
     
     
         10 . A circuit comprising:
 a peripheral component connector coupled to a peripheral component bus;   a plurality of peripheral components coupled directly to the peripheral component connector via a plurality of respective transmit/receive (TX/RX) lanes, wherein the plurality of peripheral components are further coupled directly to each other via respective transmit/receive (TX/RX) lanes and each peripheral component forwards all of the data received from the peripheral component connector to the remaining peripheral components;   wherein the peripheral component determines whether to receive the data using an address; and   wherein the plurality of peripheral components comprise at least one GPU.   
     
     
         11 . The system of  claim 10 , wherein each of the peripheral components is accessed based on an address. 
     
     
         12 . The system of  claim 10 , wherein the peripheral bus comprises a peripheral component interconnect express bus to which the peripheral components are directly coupled.