Methodology for fabricating isotropically recessed drain regions of cmos transistors

Abstract

A method for fabricating recessed drain regions of aggressively scaled CMOS devices. In this method a processing sequence of plasma etch, deposition, followed by plasma etch is used to controllably form recessed regions of the drain in the channel of a thin body, much less than 40 nm, device to enable subsequent epitaxial growth of SiGe, SiC, or other materials, and a consequent increase in the device and ring oscillator performance. A Field Effect Transistor device is also provided, which includes: a buried oxide layer; a silicon layer above the buried oxide layer; an isotropically recessed drain region; and a gate stack which includes a gate dielectric, a conductive material, and a spacer.

1 . A field effect transistor (FET) device, comprising:
 a buried oxide layer;   a silicon layer above the buried oxide layer;   a gate stack formed over a channel region of the silicon layer, the channel region having a thickness of less than 40 nanometers (nm);   a source region arranged adjacent to the silicon layer on the buried oxide layer;   a drain region arranged adjacent to the silicon layer on the buried oxide layer; and   a native oxide layer arranged along sidewalls of the gate stack and over and in contact with a portion of the source region and a portion of the drain region, wherein the source and drain regions comprise different semiconductor materials with respect to the channel region.   
     
     
         2 . The device of  claim 1 , wherein the silicon layer further comprises shallow trench isolation regions to provide isolated silicon regions. 
     
     
         3 . The device of  claim 1 , wherein the silicon layer comprises p or n-doped polysilicon. 
     
     
         4 . The device of  claim 1 , wherein a gate dielectric is formed on the silicon region and the gate stack is formed over the gate dielectric. 
     
     
         5 . The device of  claim 1 , wherein the gate stack comprises:
 doped polysilicon; and   a layer of dielectric over the native oxide.