Method for fabricating vertical channel type nonvolatile memory device

Abstract

A method for fabricating a vertical channel type nonvolatile memory device includes: stacking a plurality of interlayer insulating layers and a plurality of gate electrode conductive layers alternately over a substrate; etching the interlayer insulating layers and the gate electrode conductive layers to form a channel trench exposing the substrate; forming an undoped first channel layer over the resulting structure including the channel trench; doping the first channel layer with impurities through a plasma doping process; and filling the channel trench with a second channel layer.

What is claimed is: 
     
         1 . A method for fabricating a vertical channel type nonvolatile memory device, comprising:
 stacking a plurality of interlayer insulating layers and a plurality of conductive layers alternately over a substrate;   etching the interlayer insulating layers and the conductive layers to form a channel trench exposing the substrate;   forming an undoped first channel layer over a structure including the channel trench;   doping the undoped first channel layer with impurities through a plasma doping process to form a doped first channel layer;   performing an oxidation process of the doped first channel layer to a predetermined thickness thereby forming the buffer layer;   removing the buffer layer; and   filling the channel trench with a second channel layer.   
     
     
         2 . The method of  claim 1 , further comprising:
 forming a charge blocking layer, a charge trap layer, and a tunnel insulating layer over the structure including the channel trench before the forming of the undoped first channel layer.   
     
     
         3 . The method of  claim 1 , wherein the conductive layer is a gate electrode. 
     
     
         4 . The method of  claim 1 , further comprising:
 performing a thermal treatment process after filling the channel trench with the second channel layer.   
     
     
         5 . The method of  claim 4 , wherein the performing of a thermal treatment process includes diffusing the doped impurities of the doped first channel layer into the second channel layer. 
     
     
         6 . The method of  claim 1 , wherein the second channel layer is comprised of undoped poly silicon.