Test Pad Structure, A Pad Structure For Inspecting A Semiconductor Chip And A Wiring Substrate For A Tape Package Having The Same

Abstract

A test pad structure may include a plurality of test pads and a plurality of connection leads. A plurality of the test pads may be sequentially arranged from a wiring pattern on a substrate and arranged in rows parallel with one another. The plurality of the test pads may include a first group of test pads having at least one pad and a second group of test pads having at least two pads. A plurality of the connection leads may extend from end portions of the wiring pattern to be connected to the plurality of test pads. A plurality of the connection leads may include at least one inner lead passing between the at least two pads of the second group of the test pads and arranged in a first row closest to the first group of the test pads. The at least one inner lead may be connected to at least one pad of the at least two pads of the second group of the test pads arranged in a second row next to the first row.

What is claimed is: 
     
         1 . A test pad structure, comprising:
 a plurality of test pads sequentially arranged from a wiring pattern on a substrate and arranged in rows parallel with one another,
 the plurality of test pads including a first group of test pads having at least one pad arranged in a first row and a second group of test pads having at least two first pads and at least two second pads, the at least two first pads arranged in a second row parallel with the first row, and the at least two second pads arranged in a third row parallel with the first row; and 
   a plurality of connection leads extending from end portions of the wiring pattern to be connected to the plurality of test pads,
 the plurality of connection leads including a first group of connection leads connected to the first group of test pads and a second group of connection leads having first leads and second leads, the first leads connected to the at least two first pads, and one of the second leads passing between the at least two first pads to be connected to at least one of the at least two second pads arranged in the third row next to the second row, 
   wherein the at least two first pads arranged in the second row are spaced apart from each other by a space required for the one of the second leads, and   wherein outer edges of the at least one pad arranged in the first row and the at least two first pads arranged in the second row are contained within outer edges of the at least two second pads arranged in the third row.   
     
     
         2 . The test pad structure of  claim 1 , wherein the at least two first pads of the second group arranged in the second row have a first plane area, and the at least two second pads of the second group in the third row have a second plane area greater than the first plane area. 
     
     
         3 . The test pad structure of  claim 1 , wherein the second group of test pads are arranged to be symmetric with respect to a middle line that extends in the direction where the first group of test pads are arranged. 
     
     
         4 . The test pad structure of  claim 1 , wherein the one of the second leads comprises:
 a folded portion inclined from the direction where the first group of test pads are arranged,   the folded portion passing between the first group of the test pads and the pad of the second group of the test pads arranged in the second row.   
     
     
         5 . The test pad structure of  claim 1 , wherein the plurality of test pads are arranged in six rows. 
     
     
         6 . The test pad structure of  claim 1 , further comprising:
 a semiconductor chip mounted on the substrate,   wherein the wiring pattern is connected to at least one of input and output pads of the semiconductor chip.   
     
     
         7 . The test pad structure of  claim 6 , wherein the semiconductor chip includes a driving circuit configured to drive a display device. 
     
     
         8 . A pad structure for inspecting a semiconductor chip, comprising:
 a plurality of test pads on a substrate having a semiconductor chip mounted thereon,
 the plurality of test pads including a first group of test pads having at least one pad arranged in a first row and a second group of test pads having at least two first pads, at least two second pads and at least two third pads, the at least two first pads arranged in a second row parallel with the first row, the at least two second pads arranged in a third row parallel with the first row, and the at least two third pads arranged in a fourth row parallel with the first row; and 
   a plurality of connection leads on the substrate to connect the plurality of test pads to at least one of input and output pads of the semiconductor chip,
 the plurality of the connection leads including a first group of connection leads connected to the first group of the test pads and a second group of connection leads having first leads, second leads and third leads, the first leads connected to the at least two first pads, one of the second leads passing between the at least two first pads to be connected to one of the at least two second pads, and one of the third leads passing between the at least two first pads to be connected to one of the at least two third pads, 
   wherein the at least two first pads have a first plane area, the at least two second pads have a second plane area greater than the first plane area, and the at least two third pads have a third plane area greater than the second plane area.   
     
     
         9 . The pad structure for inspecting the semiconductor chip of  claim 8 , wherein the at least two first pads and the at least two second pads are arranged within a region that is defined between extending lines of two opposing outer edges of the at least two third pads farther away from each other. 
     
     
         10 . The pad structure for inspecting the semiconductor chip of  claim 8 , wherein the at least two first pads are spaced apart from each other by a space required for the one of the second leads and the one of the at least two third pads. 
     
     
         11 . The pad structure for inspecting the semiconductor chip of  claim 8 , wherein the second group of test pads are arranged to be symmetric with respect to a middle line that extends in the direction where the first group of the test pads are arranged. 
     
     
         12 . The pad structure for inspecting the semiconductor chip of  claim 11 , wherein each of the second and third leads comprises a folded portion inclined from the direction where the first group of test pads are arranged, the folded portion passing between the first group of the test pads and the at least one pad of the second group of pads arranged in the second row. 
     
     
         13 . The pad structure for inspecting the semiconductor chip of  claim 8 , wherein the first, second, third and fourth rows are substantially perpendicular to a direction where the plurality of test pads are arranged. 
     
     
         14 . The pad structure for inspecting the semiconductor chip of  claim 8 , wherein the plurality of test pads forms a block and a plurality of the blocks is arranged in a direction perpendicular to the direction where the plurality of test pads are arranged. 
     
     
         15 . A wiring substrate for a tape package, comprising:
 a base film including a chip-mounting region, the chip-mounting region configured to mount a semiconductor chip thereon;   a wiring pattern extending from the chip-mounting region to outside the chip-mounting region and configured to electrically connect to the semiconductor chip; and   the test pad structure of  claim 1 .   
     
     
         16 . The method of  claim 15 , wherein the semiconductor chip includes a driving circuit configured to drive a display device.