Stacked Package And Method Of Manufacturing The Same

Abstract

In one embodiment, the method includes disposing a first chip over a package substrate. The first chip has at least one first chip pad. The method further includes forming a first bonding wire connected to the first chip pad and the package substrate, and disposing a second chip over at least a portion of the first chip. The second chip has at least one second chip bonding pad. A first bonding wire is formed electrically connected to the second chip bonding pad and the first bonding wire.

1 . (canceled) 
     
     
         2 . A stacked package, comprising:
 a first chip disposed over a package substrate, the first chip having at least one first chip pad;   a first bonding wire connecting the first chip pad and the package substrate;   a second chip disposed over at least a portion of the first chip, the second chip having at least one second chip bonding pad; and   a second bonding wire electrically and physically connecting the second chip bonding pad and the first bonding wire.   
     
     
         3 . The stacked package according to  claim 2 , further comprising:
 a first protective layer covering the first chip and a second protective layer covering the second chip.   
     
     
         4 . The stacked package according to  claim 3 , wherein an interface is formed between the first protective layer and the second protective layer. 
     
     
         5 . The stacked package according to  claim 4 , wherein the first protective layer exposes at least a portion of the first bonding wire. 
     
     
         6 . The stacked package according to  claim 5 , wherein the portion of the first bonding wire is exposed at the interface. 
     
     
         7 . The stacked package according to  claim 5 , wherein the second bonding wire is directly connected to a portion of the first bonding wire, the portion being exposed by the first protective layer. 
     
     
         8 . The stacked package according to  claim 5 , wherein the portion of the first bonding wire exposed by the first protective layer has the same level with the upper surface of the first protective layer. 
     
     
         9 . A stacked package, comprising:
 a first chip disposed over a package substrate, the first chip having at least one first chip pad;   a first bonding wire connecting the first chip pad and the package substrate;   a second chip disposed over at least a portion of the first chip, the second chip having at least one second chip bonding pad;   a first protective layer covering the first chip and a second protective layer covering the second chip; and   a second bonding wire electrically connecting the second chip bonding pad and the first bonding wire,   wherein the first protective layer exposes at least a portion of the first bonding wire and the second bonding wire is directly connected to the portion of the first bonding wire, the portion being exposed by the first protective layer.