Memory controller, system including the controller, and memory delay amount control method

Abstract

A DRAM coupled to a system LSI, the DRAM receiving a test pattern from the system LSI to store the test pattern, if a power source of the system LSI is turned on, outputting the stored test pattern to the system LSI, receiving a delay set value from the system LSI, the delay set value being based on the test pattern, storing the delay set value after the power source of the system LSI is turned off and outputting the stored delay set value to the system LSI, if the power source of the system LSI is turned on again.

What is claimed is: 
     
         1 . A DRAM coupled to a system LSI, said DRAM:
 receiving a test pattern from the system LSI to store the test pattern, if a power source of the system LSI is turned on;   outputting the stored test pattern to the system LSI;   receiving a delay set value from the system LSI, the delay set value being based on the test pattern;   storing the delay set value after the power source of the system LSI is turned off; and   outputting the stored delay set value to the system LSI, if the power source of the system LSI is turned on again.   
     
     
         2 . The DRAM according to  claim 1 , further:
 receiving a program from the system LSI to store the program; and   outputting the program to the system LSI.   
     
     
         3 . The DRAM according to  claim 1 , wherein the DRAM stores the delay set value in a self-refresh mode after the power source of system LSI is turned off. 
     
     
         4 . The DRAM according to  claim 1 , wherein the DRAM outputs the stored value to the system LSI, if the power source of the system LSI is turned on again, without receiving and outputting a test pattern.