Semiconductor device and method of manufacturing the same
Abstract
A semiconductor device includes a wiring board, a semiconductor chip mounted on the wiring board, the semiconductor chip including a bump formation surface, a plurality of first bumps provided within a first region of the bump formation surface, the first bumps being arranged in a first area density, a plurality of second bumps provided within a second region of the bump formation surface, the second bumps being arranged in a second area density, and a plurality of third bumps arranged between the first region and the second region of the bump formation surface in a two-dimensional array. The plurality of third bumps are arranged in a third area density being higher than the second area density and being lower than the first area density.
Claims
exact text as granted — not AI-modified1 . A semiconductor device comprising:
a wiring board; a semiconductor chip mounted on the wiring board, the semiconductor chip including a bump formation surface; a plurality of first bumps provided within a first region of the bump formation surface, the first bumps being arranged in a first area density; a plurality of second bumps provided within a second region of the bump formation surface, the second bumps being arranged in a second area density; and a plurality of third bumps arranged between the first region and the second region of the bump formation surface in a two-dimensional array, wherein the plurality of third bumps are arranged in a third area density being higher than the second area density and being lower than the first area density.
2 . The semiconductor device according to claim 1 , wherein said wiring board includes an electrode terminal group, and said semiconductor chip is mounted on said wiring board so that a bump group faces said electrode terminal group.
3 . The semiconductor device according to claims 1 , wherein a number of the bumps formed per unit area in said third region is larger than a number of the bumps formed per unit area in said second region, and is smaller than a number of the bumps formed per unit area in said first region.
4 . The semiconductor device according to claims 1 , wherein a size of each of the bumps formed in said third region is larger than a size of each of the bumps formed in said second region.
5 . The semiconductor device according to claim 1 , wherein a bump group includes an actual bump which is electrically connected to said wiring board and a dummy bump which is not electrically connected to said wiring board.
6 . A semiconductor chip comprising a bump formation surface which faces a wiring board when mounted on said wiring board and which has a bump group formed thereon, said bump group being electrically connected to said wiring board,
wherein said bump formation surface includes: a first region in which an area density of a region having bumps arranged therein is a first density; a second region in which an area density of a region having bumps arranged therein is a second density lower than the first density; and a third region provided in a border portion between said first region and said second region, and in said third region, an area density of a region having bumps arranged therein is higher than said second density and is lower than said first density.
7 . A wiring board comprising a chip mounting surface on which a semiconductor chip is to be mounted, wherein electrode terminals are arranged on said chip mounting surface in a pattern corresponding to said bump formation surface of said semiconductor chip according to claim 5 .Join the waitlist — get patent alerts
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