Non-volatile memory unit cell with improved sensing margin and reliability

Abstract

A non-volatile memory unit cell includes a transistor pair, and first, second, third and fourth control gates. The transistor pair has a first transistor and a second transistor that are connected in parallel and of opposite types. The first transistor and the second transistor have a first floating polysilicon gate and a second floating polysilicon gate, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated. The first control gate is capacitively coupled to the first floating polysilicon gate through a first coupling junction. The second control gate is capacitively coupled to the second floating polysilicon gates through a second coupling junction. The third control gate is capacitively coupled to the first floating polysilicon gate through a first tunneling junction. The fourth control gate is capacitively coupled to the second floating polysilicon gates through a second tunneling junction.

What is claimed is: 
     
         1 . An only-one-polysilicon layer non-volatile memory unit cell comprising:
 a transistor pair having a first transistor and a second transistor that are connected in parallel and of opposite types, the first transistor and the second transistor having a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively, wherein the first floating polysilicon gate and the second floating polysilicon gate are electrically or physically isolated;   a first control gate coupled to the first floating polysilicon gate through a first capacitively coupling junction;   a second control gate coupled to the second floating polysilicon gate through a second capacitively coupling junction;   a third control gate coupled to the first floating polysilicon gate through a first tunneling junction; and   a fourth control gate coupled to the second floating polysilicon gate through a second tunneling junction.   
     
     
         2 . The only-one-polysilicon layer non-volatile memory unit cell according to  claim 1 , wherein the salicide protection layers are added on top of all the floating polysilicon gates for charge retention improvement. 
     
     
         3 . The only-one-polysilicon layer non-volatile memory unit cell according to  claim 1 , wherein the charges movement are different in first floating polysilicon gate of the first transistor and the second floating polysilicon gate of the second transistor when the non-volatile memory unit cell is at write or data deleting mode. 
     
     
         4 . The only-one-polysilicon layer non-volatile memory unit cell according to  claim 1 , wherein the charges movement are identically the same in all floating polysilicon gates of the first transistor and the second transistor when the non-volatile memory unit cell is at write or data deleting mode. 
     
     
         5 . The only-one-polysilicon layer non-volatile memory unit cell according to  claim 4 , wherein the first transistor is an N-type native transistor or receiving additional lightly doped drain (LDD) implantation to reduce the threshold voltages.