Interconnection element for electric circuits

Abstract

An interconnection element and method for making same is disclosed. The interconnection element may include a plurality of metal conductors, a plurality of solid metal bumps and a low melting point (LMP) metal layer. The solid metal bumps overly and project in a first direction away from respective ones of the conductors. Each bump has at least one edge bounding the bump in at least a second direction transverse to the first direction. The low melting point (LMP) metal layer has a first face joined to the respective ones of the conductors and bounded in the second direction by at least one edge and a second face joined to the bumps. The edges of the bumps and the LMP layer are aligned in the first direction, and the LMP metal layer has a melting temperature substantially lower than the conductors.

1 . A method of fabricating an interconnection element comprising:
 joining a metal foil extending in first and second directions with a plurality of metal conductors and a low melting point (LMP) metal layer separating the sheet from the conductors; and   patterning the metal foil to form a plurality of solid metal bumps extending away from the LMP metal layer in a third direction transverse to the first and second directions,   wherein edges of the metal bumps in the first and second directions are aligned with corresponding edges of the LMP metal layer, and   wherein the LMP metal layer has a melting temperature substantially lower than the conductors.   
     
     
         2 . The method of fabricating the interconnection element of  claim 1 , further comprising removing portions of the LMP metal layer exposed between the metal bumps. 
     
     
         3 . The method of fabricating the interconnection element of  claim 1 , further comprising joining the LMP metal layer to a dielectric element, wherein the conductors separate at least a portion of the LMP metal layer from the dielectric element. 
     
     
         4 . The method of fabricating the interconnection element of  claim 3 , wherein the LMP metal foil is comprised of copper or copper alloy. 
     
     
         5 . The method of fabricating the interconnection element of  claim 1 , wherein the step of joining the metal foil to the LMP metal layer includes pressing the metal foil onto the LMP metal layer. 
     
     
         6 . The method of fabricating the interconnection element of  claim 3 , wherein the LMP metal layer is joined to the dielectric layer and conductors by a technique selected from the group consisting of electroless plating, electroplating, displacement plating, hot air solder leveling, and cladding. 
     
     
         7 . The method of fabricating the interconnection element of  claim 1 , further including removing portions of the LMP metal layer,
 wherein the step of forming the plurality of bumps includes etching the metal foil using a first etchant having a first etching rate with respect to the metal foil and a second etching rate with respect to the LMP metal layer, the second etching rate being less than the first etching rate or zero, and   wherein the step of removing the LMP metal layer includes etching the LMP metal layer using a second etchant having a third etching rate with respect to the metal of the LMP metal layer and a fourth etching rate with respect to the metal, the fourth etching rate being less than the third etching rate or zero.   
     
     
         8 . The method of fabricating the interconnection element of  claim 7 , wherein the first etchant is an alkaline etching solution, and the second etchant is an acid etching solution. 
     
     
         9 . The method of fabricating the interconnection element of  claim 1 , wherein the LMP metal layer includes tin. 
     
     
         10 . The method of fabricating the interconnection element of  claim 1 , further comprising joining conductive pads of a microelectronic element to the metal bumps, forming an encapsulant contacting edges and at least one face of the microelectronic element and a conductive via extending through the encapsulant. 
     
     
         11 . The method of fabricating the interconnection element of  claim 10 , wherein the via is formed by a process including plating an inner wall of a hole extending through the encapsulant. 
     
     
         12 . A method of forming a microelectronic assembly including:
 forming a conductive projection on a face of a thin conductive element exposed at a surface of a substrate, the conductive projection having a base on the face of the conductive element and extending to an end remote from the face, a side wall being defined between the base and the end; and   forming a dielectric material layer over the surface of the substrate, the dielectric material layer including an outer surface spaced apart from the surface of the substrate and an opening defining a periphery that contacts the conductive projection at least along the base thereof.   
     
     
         13 . The method of  claim 12 , further including the step of forming a solder mss over the conductive projection, the solder mask being formed to extend along the end and a portion of the side wall toward the outer surface of the dielectric material layer.