Semiconductor device operating according to latency value

Abstract

Disclosed herein is a device that includes a first register temporarily storing first information indicative of a reference latency, a second register temporarily storing second information indicative of an offset latency, a third register temporarily storing third information indicative of one of first and second operation modes, and a logic circuit configured to produce latency information in response to the first information when the third information is indicative of the first operation mode and to both of the first information and the second information when the third information is indicative of the second operation mode.

1 . A device comprising:
 a first register temporarily storing first information indicative of a reference latency;   a second register temporarily storing second information indicative of an offset latency;   a third register temporarily storing third information indicative of one of first and second operation modes; and   a logic circuit configured to produce latency information in response to the first information when the third information is indicative of the first operation mode and to both of the first information and the second information when the third information is indicative of the second operation mode.   
     
     
         2 . The device as claimed in  claim 1 , wherein the latency information takes a first value when the third information is indicative of the first operation mode and a second value when the third information is indicative of the second operation mode, the first value being different from the second value. 
     
     
         3 . The device as claimed in  claim 2 , wherein the first value is greater than the second value. 
     
     
         4 . The device as claimed in  claim 1 , further comprising:
 a memory cell array including a plurality of memory cells;   at least one data terminal; and   an access circuit configured to accessing the memory cell array to select at least one of the memory cells, the access circuit being further configured to drive, in response to data stored in a selected memory cell, the data terminal in latency time indicated by the latency information.   
     
     
         5 . The device as claimed in  claim 4 , wherein the latency time in the first operation mode is different from that in the second operation mode. 
     
     
         6 . The device as claimed in  claim 4 , wherein the latency time in the first operation mode is greater than that in the second operation mode. 
     
     
         7 . A device comprising:
 a first register storing a value of a reference latency in a binary form;   a second register storing a value of an offset latency in a binary form;   a third register in which an operation mode is set;   a first logic circuit configured to subtract the value of the offset latency from the value of the reference latency to generate a first control signal indicative of a value of an adjustment latency in a binary form;   a second logic circuit configured to decode the first control signal to generate a second control signal indicative of the value of the adjustment latency in a decoded form; and   a latency counter configured to perform a count operation in synchronism with a first internal clock signal according to the second control signal when a first operation mode is set in the third register, and perform a count operation in synchronism with a second internal clock signal according to the value of the reference latency when a second operation mode is set in the third register.   
     
     
         8 . The device as claimed in  claim 7 , wherein
 the first internal clock signal is phase-controlled with respect to an external clock signal supplied from outside, and   the second internal clock signal is not phase-controlled with respect to the external clock signal.   
     
     
         9 . The device as claimed in  claim 8 , further comprising:
 a timing generation circuit configured to generate the first internal clock signal; and   a DLL circuit configured to generate the second internal clock signal,   wherein the DLL circuit is deactivated when the first operation mode is set in the third register.   
     
     
         10 . The device as claimed in  claim 9 , wherein the timing generation circuit is activated regardless of whether the first or second operation mode is set in the third register. 
     
     
         11 . The device as claimed in  claim 7 , wherein the value of the reference latency is supplied from outside through an address terminal, and the value of the offset latency is supplied from outside through a data input/output terminal. 
     
     
         12 . The device as claimed in  claim 11 , wherein the address terminal is supplied from outside with a signal indicative of the operation mode to be set in the third register. 
     
     
         13 . A device comprising:
 a first register storing a value of a reference latency;   a second register storing a value of an offset latency;   a first logic circuit configured to logically synthesize the values of the reference latency and the offset latency to generate a first control signal; and   a second logic circuit configured to decode the first control signal to generate a second control signal.   
     
     
         14 . The device as claimed in  claim 13 , wherein the first logic circuit includes a subtractor configured to subtract the value of the offset latency from the value of the reference latency. 
     
     
         15 . The device as claimed in  claim 13 , wherein the value of the reference latency is supplied from outside through an address terminal, and the value of the offset latency is supplied from outside through a data input/output terminal. 
     
     
         16 . The device as claimed in  claim 13 , wherein the second control signal indicates an adjustment latency, and the device outputting read data according to a value of the adjustment latency with reference to timing at which a read command is issued. 
     
     
         17 . The device as claimed in  claim 13 , wherein the second control signal indicates an adjustment latency, and the device inputting write data according to a value of the adjustment latency with reference to timing at which a write command is issued. 
     
     
         18 . The device as claimed in  claim 13 , wherein the second control signal indicates an adjustment latency, and the device changing an impedance of a data input/output terminal according to a value of the adjustment latency with reference to timing at which an On-Die Termination signal is issued. 
     
     
         19 . The device as claimed in  claim 13 , further comprising:
 a third register in which an operation mode is set; and   a data input/output circuit configured to control a data input/output terminal according to a value of an adjustment latency indicated by the second control signal with reference to at least one of a read command, a write command, and an On-Die Termination signal when a first operation mode is set in the third register, and control the data input/output terminal according to the value of the reference latency with reference to at least one of the read command, the write command, and the On-Die Termination signal when a second operation mode is set in the third register.   
     
     
         20 . The device as claimed in  claim 19 , further comprising:
 a first clock circuit configured to generate a first internal clock signal that is not phase-controlled based on an external clock signal supplied from outside;   a second clock circuit configured to generate a second internal clock signal that is phase-controlled based on the external clock signal; and   a latency counter configured to count the adjustment latency based on the first internal clock signal when the first operation mode is set in the third register, and count the reference latency based on the second internal clock signal when the second operation mode is set in the third register.