US2013113095A1PendingUtilityA1

Packaging substrate and fabrication method thereof

39
Assignee: CHUANG CHIEN-LUNGPriority: Nov 4, 2011Filed: May 29, 2012Published: May 9, 2013
Est. expiryNov 4, 2031(~5.3 yrs left)· nominal 20-yr term from priority
Inventors:Chien-Lung ChuangPo-Yi WuMeng-Tsung LeeYih-Jenn Jiang
H10W 72/29H10W 72/942H10W 72/952H10W 72/9415H10W 72/934H10W 72/923H10W 72/90H10W 72/01953H10W 72/01931H10W 72/019H10W 72/983H10W 72/252H10W 72/20H10W 72/221H10W 72/01255H10W 72/01235H10W 72/283H10W 74/131H10W 72/01951H10W 72/01257H10W 72/244H10W 72/242H10W 70/69H10W 70/66H10W 70/05
39
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

A packaging substrate includes a base body having at least a conductive pad on a surface thereof, a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the conductive pad and at least a second opening formed at a periphery of the first opening, and a metal layer formed on the conductive pad and the dielectric layer and extending to a sidewall of the second opening, thereby effectively eliminating side-etching of the metal layer under a solder bump.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A packaging substrate, comprising:
 a base body having at least a conductive pad on a surface;   a dielectric layer formed on the surface of the base body and having at least a first opening for exposing the at last a conductive pad and at least a second opening formed at a periphery of the first opening; and   a metal layer formed on the at least a conductive pad and the dielectric layer and extending to a sidewall of the second opening.   
     
     
         2 . The substrate of  claim 1 , further comprising at least of a solder bump disposed on the metal layer. 
     
     
         3 . The substrate of  claim 1 , wherein the at least a second opening is formed around the periphery of the at least a first opening. 
     
     
         4 . The substrate of  claim 1 , wherein the metal layer continuously covers the at least a conductive pad, a sidewall of the at least a first opening, a portion of the dielectric layer between the at least a first opening and the at least a second opening, and the sidewall of the at least a second opening. 
     
     
         5 . The substrate of  claim 1 , wherein the at least a first opening has a circular shape, the at least a second opening has a ring shape, and the at least a first and second openings are concentric. 
     
     
         6 . The substrate of  claim 1 , wherein the dielectric layer comprises a first sub-dielectric layer formed on the surface of the base body, and a second sub-dielectric layer formed on the first sub-dielectric layer and having the at least a first opening and the at least a second opening, wherein the at least a second opening exposes a portion of the first sub-dielectric layer. 
     
     
         7 . The substrate of  claim 6 , wherein the first sub-dielectric layer is made of SiN, and the second sub-dielectric layer is made of polyimide (PI) or bis-Benzo-Cyclo-Butene (BCB). 
     
     
         8 . The substrate of  claim 1 , wherein a bottom width of the at least a second opening is equal to or larger than 10 um. 
     
     
         9 . The substrate of  claim 1 , wherein a top width of the at least a second opening is equal to or larger than 20 um. 
     
     
         10 . The substrate of  claim 1 , wherein the at least a second opening has a wide top and a narrow bottom. 
     
     
         11 . The substrate of  claim 1 , wherein the metal layer is multilayered and comprises Ti/Cu. 
     
     
         12 . A fabrication method of a packaging substrate, comprising:
 providing a base body having at least a conductive pad on a surface thereof and a dielectric layer formed on the surface of the base body and at least a first opening formed in the dielectric layer for exposing the at least a conductive pad;   forming at least a second opening in the dielectric layer around a periphery of the at least a first opening;   forming a metal layer on the dielectric layer and the at least a conductive pad, wherein the metal layer extends to a sidewall of the at least a second opening; and   forming at least a solder bump on the metal layer.   
     
     
         13 . The method of  claim 12 , wherein forming the at least a solder bump on the metal layer comprises:
 forming a resist layer on the metal layer, wherein the resist layer has at least an opening corresponding in position to the at least a conductive pad and the opening has a wall located on the sidewall of the at least a second opening;   forming the at least solder bump on the metal layer in the opening of the resist layer;   removing the resist layer; and   etching a portion of the metal layer uncovered by the at least a solder bump.   
     
     
         14 . The method of  claim 13 , after removing the resist layer, further comprising reflowing the at least a solder bump. 
     
     
         15 . The method of  claim 12 , wherein the dielectric layer comprises a first sub-dielectric layer formed on the surface of the base body, and a second sub-dielectric layer formed on the first sub-dielectric layer and having the at least a first opening and the at least a second opening, wherein a portion of the first sub-dielectric layer is exposed from the at least a second opening. 
     
     
         16 . The method of  claim 15 , wherein the first sub-dielectric layer is made of SiN, and the second sub-dielectric layer is made of polyimide (PI) or bis-Benzo-Cyclo-Butene (BCB). 
     
     
         17 . The method of  claim 12 , wherein a bottom width of the at least a second opening is equal to or larger than 10 um. 
     
     
         18 . The method of  claim 12 , wherein a top width of the at least a second opening is equal to or larger than 20 um. 
     
     
         19 . The method of  claim 12 , wherein the at least a second opening has a wide top and a narrow bottom. 
     
     
         20 . The method of  claim 12 , wherein the metal layer is multilayered and comprises Ti/Cu.

Join the waitlist — get patent alerts

Track US2013113095A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.